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PRELIMINARY
JULY 2009
XR17V354
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
GENERAL DESCRIPTION
The XR17V3541 (V354) is a single chip 4-channel PCI Express (PCIe) UART (Universal Asynchronous Receiver and Transmitter), optimized for higher performance and lower power. The V354 serves as a single lane PCIe bridge to 4 indepedent enhanced 16550 compatible UARTs. The V354 is compliant to PCIe 2.0 Gen 1 (2.5GT/s). In addition to the UART channels, the V354 has 16 multi-purpose I/Os (MPIOs), a 16-bit general purpose counter/timer and a global interrupt status register to optimize interrupt servicing. Each UART of the V354 has many enhanced features such as the 256-bytes TX and RX FIFOs, programmable Fractional Baud Rate Generator, Automatic Hardware or Software Flow Control, Auto RS-485 Half-Duplex Direction Control, programmable TX and RX FIFO Trigger Levels, TX and RX FIFO Level Counters, infrared mode, and data rates up to 25Mbps. The V354 is available in a 176-pin FPBGA package (13 x 13 mm).
NOTE 1: Covered by U.S. Patents #5,649,122, #6,754,839,
#6,865,626 and #6,947,999
FEATURES
* Single 3.3V power supply * Internal buck regulator for 1.2V core * PCIe 2.0 Gen 1 compliant * x1 Link, dual simplex, 2.5Gbps in each direction * Expansion bus interface * EEPROM interface for configuration * Data read/write burst operation * Global interrupt status register for all four UARTs * Up to 25 Mbps serial data rate * 16 multi-purpose inputs/outputs (MPIOs) * 16-bit general purpose timer/counter * Sleep mode with wake-up Indicator * Four independent UART channels controlled with

16550 compatible register Set 256-byte TX and RX FIFOs Programmable TX and RX Trigger Levels TX/RX FIFO Level Counters Fractional baud rate generator Automatic RTS/CTS or DTR/DSR hardware flow control with programmable hysteresis Automatic Xon/Xoff software flow control RS-485 half duplex direction control output with programmable turn-around delay Multi-drop with Auto Address Detection Infrared (IrDA 1.1) data encoder/decoder
APPLICATIONS
* Next generation Point-of-Sale Systems * Remote Access Servers * Storage Network Management * Factory Automation and Process Control * Multi-port RS-232/RS-422/RS-485 Cards

* Software compatible to XR17C15x, XR17D15x,
XR17V25x PCI UARTs FIGURE 1. BLOCK DIAGRAM OF THE XR17V354
C o n f ig u r a t io n S pace R e g is t e r s
TX+ TXRX+ RXCLK+ CLKCLKREQ# PERST# EN485# E N IR # EECK EEDI EEDO EECS
D [ 7 :0 ]
B u c k R e g u la to r
U AR T C hannel 0
UART R egs BRG 2 5 6 - b y t e T X F IF O 64TX & R X TX & R X
T X [3 :0 ] T X [7 :0 ] R X [3 :0 ] R X [ 7 :0 ] R T S # [3 :0 ] D T R # [ 3 :0 ] C T S # [3 :0 ] D S R # [3 :0 ] D C D # [3 :0 ]
IR ENDEC
1 2 5 M H z C lo c k
2 5 6 - b y tte R X F IF O 6 4 - b y e R X F IF O
P C Ie PC I Local In t e r f a c e Bus In te r fa c e
G lo b a l C o n fig u r a tio n R e g is te r s
U AR T C hannel 1 U AR T C hannel 2 U AR T C hannel 3 2
C o n f ig u r a t io n Spa O E E P R c eM R e g is t e r s
In te r fa c e
U AR T C hannel 3 U AR T C hannel 5 U AR T C hannel 6 M u lti- p u r p o s e In A u tT /Oh a n u t s 7 U p R s C u tp n e l
R I# [ 3 : 0 ]
M P IO [ 1 5 : 0 ]
SEL CLK IN T MODE PRES
E x p a n s io n In te r f a c e
1 6 - b it T im e r /C o u n te r
- p u rp o s e In p u ts /O u t p u t s C r y s ta l O s c /B u ff e r TM RCK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XR17V354
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART FIGURE 2. 176-FPBGA PINOUT
A1 Corner
1 A B C D E F G H J K L M N P R 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Transparent Top View
1 A B C D E F G H J K L M N P R
NC NC MPIO0 MPIO2 MPIO5 GND RX+ GND TX+ GND CLKREQ# GND MPIO9 MPIO10 NC
2
NC NC NC MPIO1 MPIO4 TEST0 RXGND TXVCC12 PERST# MPIO8 MPIO12 MPIO13 RESET#
3
NC NC NC NC MPIO3 MPIO6 GND REXT GND VCC33 MPIO7 MPIO11 MPIO15 TCK TDI
4
GND NC NC GND VCC12 GND CLK+ CLKGND VCC12 GND MPIO14 TRST TDO GND
5
NC NC NC VCC33
6
NC NC NC GND
7
DSR2# CD2# RI2# VCC12
8
GND DTR2# CTS2# GND
9
RTS2# RX2 TX2 VCC33
10
TMRCK ENIR# EN485# GND
11
TEST2 TEST1 FB VCC12
12
GND GND GND GND VCC33 GND VCC12 GND VCC33 GND VCC12
13
LX VCC33 VCC33 PWRGD D1 D5 SEL RI1# DTR1# RTS1# CD0# RX0 TX0 EECK NC
14
LX VCC33 ENABLE INT D3 D6 CLK PRES DSR1# RX1 RI0# DSR0# CTS0# EEDI EECS
15
NC VCC33 D0 D2 D4 D7 MODE GND CD1# CTS1# TX1 GND DTR0# RTS0# NC
TMS TX3 RTS3# RX3
GND CTS3# DTR3# DSR3#
VCC33 CD3# NC NC
GND RI3# NC GND
VCC12 NC NC NC
GND NC NC NC
NC NC NC NC
EEDO NC NC GND
ORDERING INFORMATION
PART NUMBER XR17V354IB176-F PACKAGE 176-FPBGA OPERATING TEMPERATURE RANGE -40C to +85C DEVICE STATUS In Development
2
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
PIN DESCRIPTIONS
NAME PCIe SIGNALS CLK+ CLKTX+ TXRX+ RXCLKREQ# PERST# REXT G4 H4 J1 J2 G1 G2 L1 L2 H3 I I O O I I O I PCIe reference clock input. PCIe differential TX outputs PCIe differential RX inputs PCIe edge connector clock request PCIe edge connector reset Connect a 191 ohm 1% resistor to GND. This is used for PCIe PHY calibration. PIN # TYPE DESCRIPTION
MODEM OR SERIAL I/O INTERFACE TX0 RX0 N13 M13 O I UART channel 0 Transmit Data or infrared transmit data. UART channel 0 Receive Data or infrared receive data. Normal RXD input idles at HIGH condition. The infrared pulses can be inverted internally prior to decoding by setting FCTR bit [4]. UART channel 0 Request to Send or general purpose output (active LOW). UART channel 0 Clear to Send or general purpose input (active LOW). UART channel 0 Data Terminal Ready or general purpose output (active LOW). UART channel 0 Data Set Ready or general purpose input (active LOW). UART channel 0 Carrier Detect or general purpose input (active LOW). UART channel 0 Ring Indicator or general purpose input (active LOW). UART channel 1 Transmit Data or infrared transmit data. UART channel 1 Receive Data or infrared receive data. Normal RXD input idles at HIGH condition. The infrared pulses can be inverted prior to decoding by setting FCTR bit [4]. UART channel 1 Request to Send or general purpose output (active LOW). UART channel 1 Clear to Send or general purpose input (active LOW). UART channel 1 Data Terminal Ready or general purpose output (active LOW). UART channel 1 Data Set Ready or general purpose input (active LOW). UART channel 1 Carrier Detect or general purpose input (active LOW). UART channel 1 Ring Indicator or general purpose input (active LOW). UART channel 2 Transmit Data or infrared transmit data.
RTS0# CTS0# DTR0# DSR0# CD0# RI0# TX1 RX1
P15 N14 N15 M14 L13 L14 L15 K14
O I O I I I O I
RTS1# CTS1# DTR1# DSR1# CD1# RI1# TX2
K13 K15 J13 J14 J15 H13 C9
O I O I I I O
3
XR17V354 PIN DESCRIPTIONS
NAME RX2 PIN # B9 TYPE I
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
DESCRIPTION UART channel 2 Receive Data or infrared receive data. Normal RXD input idles at HIGH condition. The infrared pulses can be inverted prior to decoding by setting FCTR bit [4]. UART channel 2 Request to Send or general purpose output (active LOW). UART channel 2 Clear to Send or general purpose input (active LOW). UART channel 2 Data Terminal Ready or general purpose output (active LOW). UART channel 2 Data Set Ready or general purpose input (active LOW). UART channel 2 Carrier Detect or general purpose input (active LOW). UART channel 2 Ring Indicator or general purpose input (active LOW). UART channel 3 Transmit Data or infrared transmit data. UART channel 3 Receive Data or infrared receive data. Normal RXD input idles at HIGH condition. The infrared pulses can be inverted prior to decoding by setting FCTR bit [4]. UART channel 3 Request to Send or general purpose output (active LOW). UART channel 3 Clear to Send or general purpose input (active LOW). UART channel 3 Data Terminal Ready or general purpose output (active LOW). UART channel 3 Data Set Ready or general purpose input (active LOW). UART channel 3 Carrier Detect or general purpose input (active LOW). UART channel 3 Ring Indicator or general purpose input (active LOW).
RTS2# CTS2# DTR2# DSR2# CD2# RI2# TX3 RX3
A9 C8 B8 A7 B7 C7 N5 R5
O I O I I I O I
RTS3# CTS3# DTR3# DSR3# CD3# RI3#
P5 N6 P6 R6 N7 N8
O I O I I I
EXPANSION INTERFACE MODE G15 I Expansion Interface Mode Select. Connect this pin to VCC to enable master mode or when there is no slave device. Connect this pin to GND when the device is in slave mode. Expansion Interface Clock. In master mode, this pin is the clock output to the slave device. In slave mode, this pin is the clock input from the master device. The expansion interface clock is 62.5MHz. The UARTs on the slave device will need to use different baud rate generator divisors than the master device. Expansion Interface Data 7 (MSB) Expansion Interface Data 6 Expansion Interface Data 5 Expansion Interface Data 4 Expansion Interface Data 3 Expansion Interface Data 2 Expansion Interface Data 1 Expansion Interface Data 0 (LSB)
CLK
G14
I/O
D7 D6 D5 D4 D3 D2 D1 D0
F15 F14 F13 E15 E14 D15 E13 C15
I/O I/O I/O I/O I/O I/O I/O I/O
4
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
PIN DESCRIPTIONS
NAME SEL PIN # G13 TYPE I/O DESCRIPTION Expansion Interface Read/Write Select. This is the the read/write select input in the slave mode. This is the read/write select output in the master mode. This pin must be left unconnected if there is no slave device. Expansion Interface Interrupt. This is the expansion interface interrupt output in the slave mode. This is the expansion interface interrupt input in the master mode. This pin must be left unconnected if there is no slave device. Slave Present. In master mode, connect this pin to VCC if there is a slave device present. Connect this pin to GND to disable access to the slave device (slave device may or may not be present). In slave mode, this pin should be connected to GND.
INT
D14
I/O
PRES
H14
I
MPIO SIGNALS MPIO0 MPIO1 MPIO2 MPIO3 MPIO4 MPIO5 MPIO6 MPIO7 MPIO8 MPIO9 MPIO10 MPIO11 MPIO12 MPIO13 MPIO14 C1 D2 D1 E3 E2 E1 F3 L3 M2 N1 P1 M3 N2 P2 M4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Multi-purpose input/output 0. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT Multi-purpose input/output 1. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 2. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 3. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 4. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 5. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 6. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 7. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 8. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT Multi-purpose input/output 9. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 10. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 11. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 12. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 13. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 14. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
5
XR17V354 PIN DESCRIPTIONS
NAME MPIO15 EEPROM SIGNALS EECK P13 O PIN # N3 TYPE I/O
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
DESCRIPTION Multi-purpose input/output 15. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Serial clock to EEPROM. An internal clock of CLK divide by 256 is used for reading the vendor and sub-vendor ID during power up or reset. However, it can be manually clocked thru the Configuration Register REGB. Chip select to a EEPROM device like 93C46. It is manually selectable thru the Configuration Register REGB. Requires a pull-up 4.7K ohm resistor for external sensing of EEPROM during power up. Write data to EEPROM device. It is manually accessible thru the Configuration Register REGB. Read data from EEPROM device. It is manually accessible thru the Configuration Register REGB.
EECS
R14
O
EEDI EEDO JTAG SIGNALS TRESET TCK TMS TDI TDO
P14 M12
O I
N4 P3 M5 R3 P4
I I I I O
JTAG Test Reset JTAG Test Clock JTAG Test Mode Select JTAG Data Input JTAG Data Output
BUCK REGULATOR SIGNALS ENABLE LX LX FB PWRGD C14 A13 A14 C11 D13 I O O I O Connect to VCC to enable buck regulator. Connect to GND to disable buck regulator. Connect these two signals together to external 4.7uH inductor. Connect this signal to other end of external 4.7uH inductor. 47uF capacitor to GND is also required on this pin. Indicates that 1.2V core has been powered up.
ANCILLARY SIGNALS RESET# TMRCK EN485# R2 A10 C10 I I I System reset (active low). In normal operation, this signal should be HIGH. 16-bit timer/counter external clock input. Auto RS-485 mode enable (active low). This pin is sampled during power up, following a hardware reset (RST#) or soft reset (register RESET). It can be used to start up all 4 UARTs in the Auto RS-485 Half-Duplex Direction control mode. The sampled logic state is transferred to FCTR bit-5 in the UART channel. Infrared mode enable (active low). This pin is sampled during power up, following a hardware reset (RST#) or soft-reset (register RESET). It can be used to start up all 4 UARTs in the infrared mode. The sampled logic state is transferred to MCR bit-6 in the UART.
ENIR#
B10
I
6
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
PIN DESCRIPTIONS
NAME TEST0 TEST1 TEST2 VCC33 VCC33A VCC33P VCC33B VCC12 PIN # F2 B11 A11 D5, D9, E12, J12, M7 K3 B13, C13 B14, B15 D7, D11, E4, G12, K4, L12, M9 K2 A4, A8, A12, B12, C12, D4, D6, D8, D10, D12, F1, F4, F12, G3, H1, H2, H12, H15, J3, J4, K1, K12, L4, M1, M6, M8, M10, M15, R4, R8, R12 A1, A2, A3, A5, A6, A15, B1, B2, B3, B4, B5, B6, C2, C3, C4, C5, C6, D3, M11, N9, N10, N11, N12, P7, P8, P9, P10, P11, P12, R1, R7, R9, R10, R11, R13, R15 TYPE I I I Pwr Pwr Pwr Pwr Pwr DESCRIPTION Factory Test Modes. For normal operation, connect to GND.
3.3V I/O power supply. 3.3V analog PHY power supply. A ferrite bead is recommended on this pin. 3.3V power supply voltage for output stage of buck regulator. 3.3V power supply for the analog blocks of the buck regulator. 1.2V core power supply. A ferrite bead is recommended on these pins.
VCC12A GND
Pwr Pwr
1.2V analog PHY power supply. A ferrite bead is recommended on this pin. Power supply common, ground.
NC
-
No internal connection.
NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain, OT=Output Tristate, IS=Input Schmitt Trigger.
7
XR17V354 FUNCTIONAL DESCRIPTION
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
The XR17V354 (V354) integrates the functions of four independent enhanced 16550 UARTs, a general purpose 16-bit timer/counter, and 16 multi-purpose I/Os (MPIOs). Each UART channel has its own 16550 UART compatible configuration register set for individual channel control, status and data transfer. The device configuration registers include a set of four consecutive interrupt source registers that provides interrupt status for all four UARTs, timer/counter, MPIOs and a sleep wake-up indicator. Additionally, each UART channel has 256-byte of transmit and receive FIFOs, automatic RTS/CTS or DTR/DSR hardware flow control, automatic XON/XOFF, special character flow control, programmable transmit and receive FIFO trigger levels, infrared encoder/decoder (IrDA ver. 1.1), and a programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and a data rate up to 25 Mbps with the 4X sampling rate. PCIE INTERFACE AND DATA TRANSFERS This is the host interface and it meets the PCIe base specifications revision 2.0 Gen 1. The V354 also supports data read/write burst operations so the 256-byte TX or RX FIFO can be loaded or unloaded in a single transaction greatly increasing the overall system performance. LOCAL BUS CONFIGURATION SPACE REGISTERS A set of local bus configuration space register is provided. These registers provide the PCI vendor ID, device ID, sub-vendor ID, product model number, resources and capabilities which is collected by the host during the auto configuration phase that follows immediately after a power up or system reset/reboot. After the host has sorted out all devices on the bus, it defines and download the operating conditions to the cards. One of the definitions is the base address loaded into the Base Address Register (BAR) where the card will be operating in the PCI local bus memory space. All this is described in more detail in "Section 1.1, PCI LOCAL BUS CONFIGURATION SPACE REGISTERS" on page 9. EEPROM INTERFACE An external 93C46 EEPROM is used to store words of information such as PCI Vendor ID, PCI Device ID, Class Code, etc. Details of this information can be found in "Section 1.2, EEPROM Interface" on page 13. This information is only used with the plug-and-play auto configuration of the PCI local bus. These data provide automatic hardware installation onto the PCI bus. The EEPROM interface consists of 4 signals, EEDI, EEDO, EECS, and EECK. The EEPROM is not needed when auto configuration is not required in the application. However, if your design requires non-volatile memory for other purpose, it is possible to store and retrieve data on the EEPROM through a special PCI device configuration register. See application note DAN112 for its programming details.
8
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
1.0 XR17V354 INTERNAL REGISTERS The XR17V354 UART register set is very similar to the previous generation PCI UARTs. This makes the V354 software compatible with the previous generation PCI UARTs. Minimal changes are needed to the software driver of an existing Exar PCI UART driver so that it can be used with the V354 PCIe UART. There are three different sets of registers as shown in Figure 3. The PCI Local Bus Configuration Space Registers is needed for plug-and-play auto-configuration. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI local bus specification. The second register set is the Device Configuration Registers that are also accessible directly from the PCI bus for programming general operating conditions of the device and monitoring the status of various functions common to all four channels. These functions include all 4 channel UARTs' interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification and revision. And lastly, each UART channel has its own set of internal UART Configuration Registers for its own operation control and status reporting. All 4 sets of channel registers are embedded inside the device configuration registers space, which provides faster access. The second and third set of registers are mapped into 4K of the PCI bus memory address space. The following paragraphs describe all 3 sets of registers in detail. FIGURE 3. THE XR17V354 REGISTER SETS
PCI Local Bus C onfiguration Space R egisters for Plugand-Play Auto C onfiguration 0x0000 0x0080 0x0100 0x0400
D evice C onfiguration and U AR T[3:0] C onfiguration R egisters are m apped on to the Base Address R egister (BAR ) in a 4Kbyte of m em ory address space
Vendor and Sub-vendor ID and Product M odel N um ber in External EEPR O M
C hannel 0 16550 com patible registers + enhanced registers D evice C onfiguration R egisters C hannel 0 TX FIFO , R X FIFO , R X FIFO + Status Burst R eg C hannel 1 16550 com patible registers + enhanced registers
PC Ie Interface
D evice C onfiguration R egisters C hannel 1 TX FIFO , R X FIFO , R X FIFO + Status Burst R eg C hannel 2 16550 com patible registers + enhanced registers D evice C onfiguration R egisters C hannel 2 TX FIFO , R X FIFO , R X FIFO + Status Burst R eg C hannel 3 16550 com patible registers + enhanced registers D evice C onfiguration R egisters C hannel 3 TX FIFO , R X FIFO , R X FIFO + Status Burst R eg
0x0800
0x0C 00
0x0F FF
1.1
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
The PCI local bus configuration space registers are responsible for setting up the device's operating environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data from every device/card on the bus, it defines and downloads the memory mapping information to each device/ card about their individual operation memory address location and conditions. The operating memory mapped address location is downloaded into the Base Address Register (BAR) register, located at an address offset of 0x10 in the configuration space. Custom modification of certain registers is possible by using an external
9
XR17V354
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
93C46 EEPROM. The EEPROM contains the device vendor and sub-vendor data, along with 6 other words of information (see "Section 1.2, EEPROM Interface" on page 13) required by the auto-configuration setup. TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS OFFSET 0x00 BITS 31:16 TYPE EWR DESCRIPTION Device ID - No slave device on expansion interface Device ID - XR17V358 slave device on expansion interface Device ID - XR17V354 slave device on expansion interface Vendor ID (Exar) specified by PCISIG Parity error detected. Cleared by writing a logic 1. System error detected. Cleared by writing a logic 1. Unused Target Abort. DEVSEL# timing. Unemployments bus master error reporting bit Fast back to back transactions are supported Reserved Status bit 66MHz capable Capabilities List Reserved Status bits Command bits (reserved) RESET VALUE (HEX OR BINARY) 0x0354 0x8354 0x4354 0x13A8 0b 0b 00b 0b 00b 0b 0b 0b 0b 1b 0000b 0x0000
15:0 0x04 31 30 29:28 27 26:25 24 23 22 21 20 19:16 15:11, 9,7, 5, 4, 3, 2 10 8 6 1 0 0x08 31:8 7:0 0x0C 31:24 23:16 15:8 7:0
EWR RWC RWC RO RO RO RO RO RO RO RO RO RO
RWR RWR RWR RWR RO EWR RO RO RO RO RO
This bit disables the device from asserting INTx#. logic 1 = disable assertion of INTx# and logic 0 = enables assertion of INTx# SERR# driver enable. logic 1=enable driver and 0=disable driver Parity error enable. logic 1=respond to parity error and 0=ignore Command controls a device's response to mem space accesses: 0=disable mem space accesses, 1=enable mem space accesses Device's response to I/O space accesses is disabled. (0 = disable I/O space accesses) Class Code (Default is 'Simple 550 Communication Controller') Revision ID (Exar device revision number) BIST (Built-in Self Test) Header Type (a single function device with one BAR) Unimplemented Latency Timer (needed only for bus master) Unimplemented Cache Line Size
0b 0b 0b 0b 0b 0x070002 Current Rev. value 0x00 0x00 0x00 0x00
10
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS OFFSET 0x10
BITS 31:14 13:0
TYPE RWR RO RWR RO RO RO RO RO EWR EWR RO RO RO RO RO RO RO RWR RO RO RO RO RO RO RO RO RO RO RO RO
DESCRIPTION Memory Base Address Register (BAR0) Claims an 16K address space for the memory mapped UARTs including the UARTs on the expansion interface. Unimplemented Base Address Register (returns zeros) Unimplemented Base Address Register (returns zeros) Unimplemented Base Address Register (returns zeros) Unimplemented Base Address Register (returns zeros) Unimplemented Base Address Register (returns zeros) Reserved Subsystem ID (write from external EEPROM by customer) Subsystem Vendor ID (write from external EEPROM by customer) Expansion ROM Base Address (Unimplemented) Reserved (returns zeros) Capability Pointer Reserved (returns zeros) Unimplemented MAXLAT Unimplemented MINGNT Interrupt Pin, use INTA#. Interrupt Line. Not implemented or not applicable (return zeros) CSR Not implemented or not applicable (return zeros) Not implemented or not applicable (return zeros) 64-bit address capable Next Capability Pointer MSI Capable Capability ID Not implemented or not applicable (return zeros) Not implemented or not applicable (return zeros) Next Capability Pointer MSI-X Capable Capability ID Not implemented or not applicable (return zeros)
RESET VALUE (HEX OR BINARY) 0x00000 0x0000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000 0x0000 0x00000000 0x000000 0x50 0x00000000 0x00 0x00 0x01 0xXX 0x00000000 0x02106160 0x00000000 0x00000000 0x0080 0x78 0x05 0x00000000 0x0000 0x78 0x11 0x00000000
0x14 0x18h 0x1C 0x20 0x24 0x28 0x2C
31:0 31:0 31:0 31:0 31:0 31:0 31:16 15:0
0x30 0x34
31:0 31:8 7:0
0x38 0x3C
31:0 31:24 23:16 15:8 7:0
0x40 0x44 0x48 0x4C 0x50
31:0 31:0 31:0 31:0 31:16 15:8 7:0
0x54-0x67 31:0 0x68 31:16 15:8 7:0 0x6C-0x77 31:0
11
XR17V354
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS OFFSET 0x78 BITS 31:16 15:8 7:0 0x7C 0x80 31:0 31:16 15:8 7:0 0x84 31:16 15:8 7:0 0x88 31:16 15:8 7:0 0x8C 31:24 23:22 21:18 17:15 14:12 11:10 9:4 3:0 0x90 31:21 20 19 18 17:15 14:10 9:4 3:0 0x94 31:0 TYPE RO RO RO RO RO RO RO RO RO RO RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO DESCRIPTION PME# support (PME# can be asserted from D3hot and D0) PCI Power Management 1.2 Next Capability Pointer Power Management Capability ID No soft reset when transitioning from D3hot to D0 state PCI Express 2.0 capable endpoint, Interrupt Message Number 1 Next Capability Pointer PCI Express Capability ID Not implemented or not applicable (return zeros) Role-Based Error Reporting 256 bytes max payload size Not implemented or not applicable (return zeros) 512 bytes max read request, Enable No Snoop 256 bytes max TLP payload size Port Number Not implemented or not applicable (return zeros) Not implemented or not applicable (return zeros) L1 Exit Latency < 1 us L0s Exit Latency < 64 ns Active State Power Management (ASPM) Support L0s and L1 Supported x1 max Link Width 2.5GT/s Link speed supported Not implemented or not applicable (return zeros) Data Link Layer Active Reporting capable Surprise Down Error Reporting not supported Reference clock must not be removed. L1 Exit Latency - 2 us to less than 4 us Not implemented or not applicable (return zeros) x1 negotiated Link Width Current Link Speed is 2.5GT/s PCIe Capability Offset 0x14 - Slot Capabilities Register Not implemented or not applicable (return zeros)
RESET VALUE (HEX OR BINARY) 0x4803 0x80 0x01 0x00000008 0x0202 0x00 0x10 0x0000 0x80 0x01 0x0000 0x28 0x10 0x01 00b 0000b 000b 000b 11b 000001b 0001b 00000000000b 1b 0b 0b 010b 00000b 000001b 0001b 0x00040000 0x00000000
0x98-0xAF 31:0
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HIGH PERFORMANCE QUAD PCI-EXPRESS UART TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS OFFSET 0xB0
BITS 31:0
TYPE RO RO RO RO RO
DESCRIPTION PCIe Capability Offset 0x30 - Link Status2/Control2 Not implemented or not applicable (return zeros) VC Resource Capability Register Not implemented or not applicable (return zeros) VC Offset 0x4
RESET VALUE (HEX OR BINARY) 0x00010001 0x00000000 0x00010002 0x00000000 0x8000000FF
0xB4-0xFF 31:0 0x100 0x1040x113 0x114 31:0 31:0 31:0
NOTE: EWR=Read/Write from external EEPROM. RWR=Read/Write. RO= Read Only. RWC=Read/Write-Clear.
1.2
EEPROM Interface
The V354 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This interface is provided in order to program the registers in the PCI Configuration Space of the PCI UART during power-up. The EEPROM must be organized into address/data pairs. The first word of the pair is the address and the second word is the data. Table 2 below shows the format of the 16-bit address: TABLE 2: EEPROM ADDRESS BIT DEFINITIONS
BIT(S) 15 DEFINITION Parity Bit - Odd parity over entire address/data pair If there is a parity error, it will be reported in bit-3 of the REGB register in the Device Configuration Registers (offset 0x08E). Final Address If 1, this will be the last data to be read. If 0, there will be more data to be read after this. Reserved - Bits must be '0' Target Address - See Table 3
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13:8 7:0
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Table 3 shows the Target Addresses available for programming into bits 7:0 of the 16-bit address word. All other Target Addresses are reserved and must not be used. TABLE 3: TARGET ADDRESS FOR EEPROM VALUES
TARGET ADDRESS 0x00 0x01 DATA Vendor ID Device ID 0x13A8 0x0354 - No slave 0x4354 - XR17V354 slave present 0x8354 - XR17V358 slave present 0x0200 0x0700 0x0000 0x0000 EXAR DEFAULT
0x02 0x03 0x04 0x05
Class Code [7:0] lower 8-bits are reserved Class Code [23:8] Subsystem Vendor ID Subsystem ID
The second 16-bit word of the address/data pair is the data. The default values are shown in Table 3. The address/data pairs can be in any order. Only the contents which need to be changed from the Exar defaults need to be included in the EEPROM. 1.3 Device Internal Register Sets The Device Configuration Registers and the four individual UART Configuration Registers of the V354 occupy 4K of PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. The UART Configuration Registers are mapped into 4 address blocks where each UART channel occupies 1024 bytes memory space for its own registers that include the 16550 compatible registers. The Device Configuration Registers are accessible from all UART channels. However, not all bits can be controlled by all channels. The UART channel can only control the 8XMODE, 4XMODE, RESET and SLEEP register bits that apply to that particular channel. For example, this prevents channel 0 from accidentally resetting channel 1. All these registers can be accessed in 8, 16, 24 or 32 bits width depending on the starting address given by the host at the beginning of the bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bits format in special locations given in the Table 4 below. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer is automatically bumped to the next sequential data location either in byte, word or DWORD. One special case applies to the receive data unloading when reading the receive data together with its LSR register content. The host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated error flags. These special registers are further discussed in "Section 2.1, FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT" on page 29.
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HIGH PERFORMANCE QUAD PCI-EXPRESS UART TABLE 4: XR17V354 UART AND DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS 0x0000 - 0x000F 0x0010 - 0x007F 0x0080 - 0x009A 0x009B - 0x00FF 0x0100 - 0x01FF 0x0100 - 0x01FF 0x0200 - 0x03FF
MEMORY SPACE UART channel 0 Regs Reserved DEVICE CONFIGURATION REGISTERS Reserved UART 0 - Read FIFO UART 0 - Write FIFO UART 0 - Read FIFO with errors
READ/WRITE
COMMENT
(Table 13 & First 8 regs are 16550 compatible
Table 14)
(Table 5)
Read-Only Write-Only Read-Only
256 bytes of RX FIFO data 256 bytes of TX FIFO data 256 bytes of RX FIFO data + LSR
0x0400 - 0x040F 0x0410 - 0x047F 0x0480 - 0x049A 0x049B - 0x04FF 0x0500 - 0x05FF 0x0500 - 0x05FF 0x0600 - 0x07FF
UART channel 1 Regs Reserved DEVICE CONFIGURATION REGISTERS Reserved UART 1 - Read FIFO UART 1 - Write FIFO UART 1 - Read FIFO with errors
(Table 13 & First 8 regs are 16550 compatible
Table 14)
(Table 5)
Read-Only Write-Only Read-Only
256 bytes of RX FIFO data 256 bytes of TX FIFO data 256 bytes of RX FIFO data + LSR
0x0800 - 0x080F 0x0810 - 0x087F 0x0880 - 0x089A 0x089B - 0x08FF 0x0900 - 0x09FF 0x0900 - 0x09FF 0x0A00 - 0x0BFF
UART channel 2 Regs Reserved DEVICE CONFIGURATION REGISTERS Reserved UART 2 - Read FIFO UART 2 - Write FIFO UART 2 - Read FIFO with errors
(Table 13 & First 8 regs are 16550 compatible
Table 14)
(Table 5)
Read-Only Write-Only Read-Only
256 bytes of RX FIFO data 256 bytes of TX FIFO data 256 bytes of RX FIFO data + LSR
0x0C00 - 0x0C0F 0x0C10 - 0x0C7F 0x0C80 - 0x0C9A 0x0C9B - 0x0CFF 0x0D00 - 0x0DFF 0x0D00 - 0x0DFF 0x0E00 - 0x0FFF
UART channel 3 Regs Reserved DEVICE CONFIGURATION REGISTERS Reserved UART 3 - Read FIFO UART 3 - Write FIFO UART 3 - Read FIFO with errors
(Table 13 & First 8 regs are 16550 compatible
Table 14)
(Table 5)
Read-Only Write-Only Read-Only
256 bytes of RX FIFO data 256 bytes of TX FIFO data 256 bytes of RX FIFO data + LSR
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1.4 Device Configuration Registers
PRELIMINARY
REV. P1.0.2
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The Device Configuration Registers provide easy programming of general operating parameters to the V354 and for monitoring the status of various functions. These registers control or report on all 4 channel UARTs functions that include interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-reset control, and device identification and revision, and others. Tables 5 and 6 below show these registers in BYTE and DWORD alignment. Each of these registers is described in detail in the following paragraphs. TABLE 5: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
ADDRESS [A7:A0] Ox080 Ox081 Ox082 Ox083 REGISTER INT0 [7:0] INT1 [15:8] INT2 [23:16] INT3 [31:24] READ/WRITE COMMENT Read-only Interrupt [7:0] Read-only Read-only Read-only
RESET STATE
Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00
Ox084 Ox085 Ox086 Ox087
TIMERCNTL REGA TIMERLSB TIMERMSB
Read/Write Timer Control Reserved Read/Write Timer LSB Read/Write Timer MSB
Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0]= 0x00 Bits [7:0]= 0x00
Individual UART channels can only control the bit pertaining to that channel in the registers at address offset 0x088-0x08B. Ox088 Ox089 Ox08A Ox08B 8XMODE 4XMODE RESET SLEEP Read/Write Read/Write Write-only Self clear bits after executing Reset Read/Write Sleep mode Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0]= 0x00
Ox08C Ox08D Ox08E Ox08F
DREV DVID REGB MPIOINT[7:0]
Read-only Device revision Read-only Device identification Read/Write EEPROM control Read/Write MPIO[7:0] interrupt mask
Bits [7:0] = Current Rev. Bits [7:0] = 0x84 Bits [7:0] = 0x00 Bits [7:0] = 0x00
Ox090 Ox091 Ox092 Ox093
MPIOLVL[7:0] MPIO3T[7:0] MPIOINV[7:0] MPIOSEL[7:0]
Read/Write MPIO[7:0] level control Read/Write MPIO[7:0] output control Read/Write MPIO[7:0] input polarity select Read/Write MPIO[7:0] select
Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0xFF
0x094 Ox095 Ox096 Ox097
MPIOOD[7:0] MPIOINT[15:8] MPIOLVL[15:8] MPIO3T[15:8]
Read/Write MPIO[7:0] open-drain output control Read/Write MPIO[15:8] interrupt mask Read/Write MPIO[15:8] level control Read/Write MPIO[15:8] output control
Bits [7:0] = 0x00 Bits [15:8] = 0x00 Bits [15:8] = 0x00 Bits [15:8] = 0x00
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HIGH PERFORMANCE QUAD PCI-EXPRESS UART TABLE 5: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
ADDRESS [A7:A0] Ox098 Ox099 0x09A 0x09B
REGISTER MPIOINV[15:8] MPIOSEL[15:8] MPIOOD[15:8] Reserved
READ/WRITE COMMENT Read/Write MPIO[15:8] input polarity select Read/Write MPIO[15:8] select Read/Write MPIO[15:8] open-drain output control
RESET STATE
Bits [15:8] = 0x00 Bits [15:8] = 0xFF Bits [15:8] = 0x00 0x00
TABLE 6: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT
ADDRESS 0x0080-0x0083 0x0084-0x0087 0x0088-0x008B 0x008C-0x008F 0x0090-0x0093 0x0094-0x0097 0x0098-0x009B REGISTER INTERRUPT (read-only) TIMER (read/write) ANCILLARY1 (read/write) ANCILLARY2 (read-only) MPIO1 (read/write) MPIO2 (read/write) MPIO3 (read/write) BYTE 3 [31:24] INT3 TIMERMSB SLEEP MPIOINT[7:0] MPIOSEL[7:0] MPIO3T[7:0] Reserved BYTE 2 [23:16] INT2 TIMERLSB RESET REGB MPIOINV[7:0] MPIOLVL[15:8] MPIOOD[15:8] BYTE 1 [15:8] INT1 Reserved 4XMODE DVID MPIO3T[7:0] MPIOINT[15:8] MPIOSEL[15:8] BYTE 0 [7:0] INT0 TIMERCNTL 8XMODE DREV MPIOLVL[7:0] MPIOOD[7:0] MPIOINV[15:8]
1.4.1
The Global Interrupt Registers - INT0, INT1, INT2 and INT3
The XR17V354 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme is an 4-bit indicator representing all 4 channels with each bit representing each channel from 0 to 3. This permits the interrupt service routine to quickly determine which UART channels need servicing so that it can go to the appropriate UART channel interrupt service routines. INT0 bit [0] represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or modem port status requires service. Other bits in the INT0 register provide indication for the other channels with bit [3] representing UART channel 3 respectively. The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART's transmitter, receiver, line status, modem port status. INT1, INT2 and INT3 registers provide the 24-bit interrupt status for all 4 channels. bits [10:8] representing channel 0 and bits [19:17] representing channel 3 respectively. The rest bits are reserved. All 4 channel interrupts status are available with a single DWORD read operation. This feature allows the host another method to quickly service the interrupts, thus reducing the service interval and host bandwidth requirement. Note that the interrupts reported in this register is specific to each UART channel. If there is a global interrupt such as the wake-up interrupt, timer/counter interrupt or MPIO interrupt, they would be reported in the 3-bit code for channel 0 in INT1. GLOBAL INTERRUPT REGISTER (DWORD)
INT3 [31:24] INT2 [23:16]
[default 0x00-00-00-00]
INT0 [7:0]
INT1 [15:8]
All bits start up zero. A special interrupt condition is generated by the V354 upon awakening from sleep after all four channels were put to sleep mode earlier. This wake-up interrupt is cleared by a read to the INT0 register. Figure 4 shows the 4-byte interrupt register and its make up.
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XR17V354
INT0 [7:0] Channel Interrupt Indicator
PRELIMINARY
REV. P1.0.2
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Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and bit [3] indicates channel 3. The upper four bits INT0[7:4] are reserved. Logic 1 indicates the channel N [3:0] has called for service. The interrupt bit clears after reading the appropriate register of the interrupting channel register, see Interrupt Clearing section. The INT0 register provides individual status for each channel
INT0 Register Individual UART Channel Interrupt Status Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0 0 0 0 0 Bit-3 Bit-2 Bit-1 Bit-0
INT3, INT2 and INT1 [31:8] 3-bit Channel Interrupt Encoding Each channel's interrupt is encoded into 3 bits for receive, transmit, and status. Bits [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. The 3-bit encoding and their priority order are shown below in Table 7. The wake-up interrupt, timer/counter interrupt and MPIO interrupt are only reported in channel 0 of INT1 (bits[10:8]). These interrupts are not reported in any other location. FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3
Interrupt Registers, INT0, INT1, INT2 and INT3
INT3 Register Reserved 0 0 0 0 Reserved 0 0 0 Reserved 0 0 0 INT2 Register Reserved 0 0 Bit N+2 Channel-3 Bit N+1 Bit N Bit N+2 Channel-2 Bit N+1 Bit N Bit N+2 INT1 Register Channel-1 Bit N+1 Bit N Bit N+2 Channel-0 Bit N+1 Bit N
INT0 Register Rsvd Rsvd Rsvd Rsvd 0 0 0 0 Ch-3 Ch-2 Ch-1 Ch-0 Bit-3 Bit-2 Bit-1 Bit-0
TABLE 7: UART CHANNEL [3:0] INTERRUPT SOURCE ENCODING
PRIORITY x 1 2 3 4 5 6 7 BIT[N+2] 0 0 0 0 1 1 1 1 BIT[N+1] 0 0 1 1 0 0 1 1 BIT[N] 0 1 0 1 0 1 0 1 INTERRUPT SOURCE(S) None or wake-up indicator (wake-up indicator is reported in channel 0 only) RXRDY and RX Line Status (logic OR of LSR[4:1]) RXRDY Time-out TXRDY, THR or TSR (auto RS485 mode) empty MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected Reserved. MPIO pin(s). Reported in channel 0 only. Timer/Counter. Reported in channel 0 only.
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HIGH PERFORMANCE QUAD PCI-EXPRESS UART TABLE 8: UART CHANNEL [3:0] INTERRUPT CLEARING
Wake-up Indicator is cleared by reading the INT0 register. RXRDY and RXRDY Time-out is cleared by reading data in the RX FIFO. RX Line Status interrupt clears after reading the LSR register that is in the UART channel register set. TXRDY interrupt clears after reading ISR register that is in the UART channel register set. Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set. RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set. Xoff/Xon delta and special character detect interrupt clears after reading the ISR register that is in the UART channel register set. TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set. MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
1.4.2
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-00-00)
The XR17V354 has a general purpose 16-bit timer/counter. The internal 125MHz clock (master mode) or 62.5MHz clock (slave mode) or the external clock at the TMRCK input pin can be selected as the clock source for the timer/counter. The timer can be set to be a single-shot for a one-time event or re-triggerable for a periodic signal. An interrupt may be generated when the timer times out and will show up as a Channel 0 interrupt (see Table 7). It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. The TIMERCNTL register provides the Timer commands such as start/stop, as shown in Table 9 below. The time-out output of the Timer can also be optionally routed to the MPIO[0] pin. The block diagram of the Timer/Counter circuit is shown below: FIGURE 5. TIMER/COUNTER CIRCUIT
TIMERMSB and TIMERLSB (16-bit Value)
TMRCK 125MHz/62.5MHz 1 0
16-Bit Timer/Counter
Timer Output
1 0
MPIO[0]
Clock Select Start/Stop Single shot/Re-triggerable Timer Interrupt Enable/ Disable Route/De-route to MPIO[0]
MPIOLVL[0] Timer Interrupt 1 0 Timer Interrupt No Interrupt
TIMERCNTL COMMANDS
TIMERMSB [31:24] and TIMERLSB [23:16] registers The concatentaion of the 8-bit registers TIMERMSB and TIMERLSB forms a 16-bit value which decides the time-out period of the Timer, per the following equation: Timer output frequency = Timer input clock / 16-bit Timer value The least-significant bit of the timer is being bit [0] of the TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Notice that these registers do not hold the current counter value when read. Default value is zero (timer disabled) upon powerup and reset. The 'Reset Timer' command does not have any effect on this register.
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HIGH PERFORMANCE QUAD PCI-EXPRESS UART
1 6 -B it T im e r/C o u n te r P ro g ra m m a b le R e g iste rs
TIM ERM SB Register B it-1 5 B it-1 4 B it-1 3 B it-1 2 B it-1 1 B it-1 0 B it-9 B it-8 B it-7 B it-6 TIM ERLSB Register B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
REGA [15:8] Register Reserved. TIMERCNTL [7:0] Register The bits [3:0] of this register are used to issue commands. The commands are self-clearing, so reading this register does not show the last written command. Reading this register returns a value of 0x01 when the Timer interrupt is enabled and there is a pending Timer interrupt. It returns a value of 0x00 at all other times. The default settings of the Timer, upon power-up, a hardware reset or upon the issue of a 'Timer Reset' command are:

Timer Interrupt Disabled Re-triggerable mode selected Internal 125MHz clock (master) or 62.5MHz clock (slave) selected as clock source Timer output not routed to MPIO[0] Timer stopped TABLE 9: TIMER CONTROL REGISTERS
TIMERCNTL [7:4] TIMERCNTL [3:0]
Reserved These bits are used to invoke a series of commands that control the function of the Timer/Counter. The commands 1100 to 1111 are reserved. 0001: Enable Timer Interrupt 0010: Disable Timer Interrupt 0011: Select One-shot mode 0100: Select Re-triggerable mode 0101: Select Internal 125MHz clock (master) or 62.5MHz clock (slave) as clock input for the Timer 0110: Select External Clock input through the TMRCK pin for the Timer 0111: Route Timer output to MPIO[0] pin 1000: De-route Timer output from MPIO[0] 1001: Start Timer 1010: Stop Timer 1011: Reset Timer
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TIMER OPERATION The following paragraphs describe the operation of the 16-bit Timer/Counter. The following conventions will be used in this discussion:

'N' is the 16-bit value programmed in the TIMER MSB, LSB registers P +Q = N, where 'P' and 'Q' are approximately half of 'N'. If N is even, P = Q = N/2. If N is odd, P = (N - 1)/2 and Q = (N + 1)/2. `N' can take any value from 0x0002 to 0xFFFF.
Timer Operation in One-Shot Mode: In the one-shot mode, the Timer output will stay HIGH when started (default state) and will continue to stay HIGH until it times out (reaches the terminal count of `N' clocks), at which time it will become LOW and stay LOW. If the Timer is re-started before the Timer times out, the counter is reset and the Timer will wait for another time-out period before setting its output LOW (See Figure 6). If the Timer times out, re-starting the Timer does not have any effect and a 'Stop Timer' command needs to be issued first which will set the Timer output to its default HIGH state. The Timer must be programmed while it is stopped since the following operations are blocked after the Timer has been started:

Any write to TIMER MSB, LSB registers Issue of any command other than 'Start Timer', 'Stop Timer' and 'Reset Timer'
Timer Operation in Re-triggerable Mode: In the re-triggerable mode, when the Timer is started, the Timer output will stay HIGH until it reaches half of the terminal count N (= P clocks) and toggle LOW and stay LOW for a similar amount of time (Q clocks). The above step will keep repeating until the Timer is stopped at which time the output will become HIGH (default state). See Figure 6. Also, after the Timer is started, re-starting the Timer does not have any effect in retriggerable mode. The Timer must be programmed while it is stopped since the following operations are blocked when the Timer is running:

Any write to TIMER MSB, LSB registers Issue of any command other than 'Stop Timer' and 'Reset Timer' ('Start Timer' is not allowed)
Routing the Timer Output to MPIO[0] Pin: MPIO[0] pin is by default (on power up or reset, for example) an input. However, whenever the Timer output is routed to MPIO[0] pin,

MPIO[0] will be automatically selected as an output MPIO[0] will become HIGH (the default state of Timer output) All MPIO control registers (MPIOLVL, MPIOSEL etc) lose control over MPIO[0] and get the control back only when the Timer output is de-routed from MPIO[0].
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HIGH PERFORMANCE QUAD PCI-EXPRESS UART FIGURE 6. TIMER OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES
START TIMER COMMAND ISSUED START TIMER COMMANDS ISSUED: LESS THAN 'N' CLOCKS BETWEEN SUCCESSIVE COMMANDS START TIMER COMMAND ISSUED STOP TIMER COMMAND ISSUED
TIMER Output in One-Shot Mode
'N' Clocks
< 'N' Clocks
< 'N' Clocks
TIMER Output in Re-triggerable Mode
After 'P' clocks
After 'P' clocks
After 'P' clocks
After 'P' clocks
After 'P' clocks
After 'Q' clocks
After 'Q' clocks
After 'Q' clocks
After 'Q' clocks
Timer Interrupt In the one-shot mode, the Timer will issue an interrupt upon timing out which is 'N' clocks after the Timer is started. In the re-triggerable mode, the Timer will keep issuing an interrupt every 'N' clocks which is on every rising edge of the Timer output. The Timer interrupt can be cleared by reading the TIMERCNTL register or when a Timer Reset command is issued which brings the Timer back to its default settings. The TIMERCNTL will read a value of 0x01 when the Timer interrupt is enabled and there is a pending interrupt. It reads a value of 0x00 at all other times. Stopping the Timer does not clear the interrupt and neither does subsequent restarting. FIGURE 7. INTERRUPT OUTPUT (ACTIVE LOW) IN ONE-SHOT AND RE-TRIGGERABLE MODES
Timer Started Timer Timed Out TIMERCNTL read
One-shot Mode
Timer Timed TIMERCNTL Out read
Timer Timed Out
Re-triggerable Mode
1.4.3
8XMODE [7:0] (default 0x00)
Each bit selects 8X or 16X sampling rate for that UART channel. The 8XMODE register is accessible from the Device Configuration Registers in all UART channels but the UART channel can only control the bit for that channel. For example, bit [0] is for channel 0 and can only be controlled by channel 0. All other bits are readonly in channel 0. Logic 0 (default) selects normal 16X sampling (and 4XMODE = 0x00) with logic one selects
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8X sampling rate. Transmit and receive data rates will double by selecting 8X. If using the 4XMODE, the corresponding bit in this register should be logic 0
8XMODE Register Individual UART Channel 8X Clock Mode Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0 0 0 0 Ch-3 Ch-2 Ch-1 Ch-0
1.4.4
4XMODE [15:8] (default 0x00)
Each bit selects 4X or 16X sampling rate for that UART channel. The 4XMODE register is accessible from the Device Configuration Registers in all UART channels but the UART channel can only control the bit for that channel. For example, bit [0] is channel 0 and can only be controlled by channel 0. All other bits are read-only in channel 0. Logic 0 (default) selects normal 16X sampling (and 8XMODE = 0x00) with logic one selects 4X sampling rate. Transmit and receive data rates will quadruple by selecting 4X. If using the 8XMODE, the corresponding bit in this register should be logic 0
4XMODE Register Individual UART Channel 4X Clock Mode Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0 0 0 0 Ch-3 Ch-2 Ch-1 Ch-0
RESET [23:16] (default 0x00) The 8-bit RESET register provides the software with the ability to reset the UART(s) when there is a need. The RESET register is accessible from the Device Configuration Registers in all UART channels but the UART channel can only control the bit for that channel. For example, writing 0xFF to the RESET register in channel 0 will only reset channel 0. Each bit is self-clearing after it is written a logic 1 to perform a reset to that channel. All registers in that channel will be reset to the default condition, see Table 21 for details. .
RESET Register Individual UART Channel Reset Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0 0 0 0 Ch-3 Ch-2 Ch-1 Ch-0
1.4.5
SLEEP [31:24] (default 0x00)
SLEEP Register Individual UART Channel Sleep Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0 0 0 0 Ch-3 Ch-2 Ch-1 Ch-0
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XR17V354
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
The 8-bit SLEEP register enables each UART separately to enter Sleep mode. The SLEEP register is accessible from the Device Configuration Registers in all UART channels but the UART channel can only control the bit for that channel. For example, writing 0xFF to the SLEEP register in channel 0 will only enable the sleep mode for channel 0. Sleep mode reduces power consumption when the system needs to put the UART(s) to idle. The UART enters sleep mode when the following conditions are satisfied after the sleep mode is enabled (Logic 0 (default) is to disable and logic 1 is to enable sleep mode):

Transmitter and Receiver are empty (LSR[6]=1, LSR[0]=0) RX pin is idling at a HIGH in normal mode or a LOW in infrared mode The modem inputs (CTS#, DSR#, CD# and RI#) are steady at either HIGH or LOW (MSR bits [3:0] = 0x0) A receive data start bit transition (HIGH to LOW in normal mode or from LOW to HIGH in infrared mode) A data byte is loaded into the transmitter A change of logic state on any of the modem inputs so that any of the delta bits (MSR bits[3:0]) is set (RI# delta bit is only set on the rising edge)
The V354 is awakened by any of the following events occurring at any of the 4 UART channels:

A receive data start bit transition will not wake up the UART if the Multidrop mode is disabled (DLD[6] = 0) and the receiver is disabled (MSR[2] = 1, MSR[0] = 0). A special interrupt is generated with an indication of no pending interrupt. The V354 will return to sleep mode automatically after all interrupting conditions have been serviced and cleared. It will stay in the sleep mode of operation until it is disabled by resetting the SLEEP register bits. 1.4.6 Device Identification and Revision
There are two internal registers that provide device identification and revision, DVID and DREV registers. The 8-bit content in the DVID register provides device identification. A return value of 0x84 from this register indicates the device is a XR17V354. The DREV register returns an 8-bit value of 0x01 for revision A with 0x02 equals to revision B and so on. This information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes. DVID [15:8] Device identification for the type of UART. The Device ID of the XR17V354 is 0x84. DREV [7:0] Revision number of the XR17V354. A 0x01 represents "revision-A" with 0x02 for rev-B and so on. REGB [23:16] (default 0x00) REGB register provides a control for simultaneous write to all 4 UARTs configuration register or individually. This is very useful for device initialization in the power up and reset routines. Also, the register provides a facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications, the user can use this facility to store proprietary data in an external EEPROM. 1.4.7 REGB Register
Logic 0 (default) write to each UART configuration registers individually. Logic 1 enables simultaneous write to all 4 UARTs configuration register. REGB[17](Read/Write) Logic 0 (default) - wake-up interrupt is generated when UART exits sleep mode. Logic 1 - No wake-up interrupt is generated when UART exits sleep mode.
REGB[16](Read/Write)
24
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART REGB Register
Logic 0 (default) - Global interrupt enable. Interrupts to PCI host are enabled. Logic 1 - Global interrupt disable. Interrupts to PCI host are disabled.
1.4.7
REGB[18](Read/Write
REGB[19](Read-Only)
Logic 0 - EEPROM load is valid. Logic 1 - EEPROM load error caused by one of the following conditions: EEPROM not attached, final bit not found, parity error detected.
REGB[20] (Write-Only) REGB[21] (Write-Only) REGB[22] (Write-Only) REGB[23] (Read-Only)
Control the EECK, clock, output on the EEPROM interface. Control the EECS, chips select, output to the EEPROM device. EEDI data input. Write data to the EEPROM device. EEDO data output. Read data from the EEPROM device.
1.4.8
Multi-Purpose Inputs and Outputs
The V354 provides 16 multi-purpose inputs/outputs MPIO[15:0] for general use. Each pin can be programmed to be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to generate an interrupt. The outputs can be set to be normal HIGH or LOW state, 3-state, or open drain. Their functions and definitions are programmed through 6 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV, MPIOSEL, and MPIOOD. If all 16 pins are set for inputs, all 16 interrupts would be ORed together. The ORed interrupt is reported in the channel 0 UART interrupt status, see Interrupt Status Register. The pins may also be programmed to be outputs and to the 3-state condition for signal sharing. The MPIO[0] pin can be programmed to show the Timer output. When it is programmed to be the Timer output, all the above 5 registers lose control over the MPIO[0] pin. For details on Timer output, please see "Section 1.4.2, General Purpose 16-bit Timer/ Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default 0xXX-XX-00-00)" on page 19. 1.4.9 MPIO REGISTERS
25
XR17V354
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
There are 2 sets of 6 registers that select, control and monitor the 16 multipurpose inputs and outputs. Figure 8 shows the internal circuitry. FIGURE 8. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT
M P IO IN T [15:0]
IN T
AND
R ising E dge D etection
AND
1 M P IO LV L [15:0]
R ea d In pu t L e vel
M P IO P in [15:0] 0
M P IO IN V [15:0]
(Inp u t In versio n E n a ble = 1)
M P IO LV L [15:0]
(O u tpu t L e vel)
M P IO O D [15:0]
(O p en-D ra in E n a ble = 1 ) AND OR
M P IO 3T [15:0]
(3-sta te E na b le = 1)
M P IO S E L [15:0]
(S ele ct In pu t=1 , O u tp ut=0 )
26
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
MPIOINT [15:0] (default 0x00) The MPIOINT register enables the multipurpose input pin interrupt. If an MPIO pin is selected by MPIOSEL as an input, then it can be selected to generate an interrupt. MPIOINT bit[0] enables input pin MPIO0 for interrupt, and bit [7] enables input pin 7. No interrupt is enable if the pin is selected to be an output. The interrupt is edge sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after a read to register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active LOW or active HIGH. Logic 0 (default) disables the pin's interrupt and logic 1 enables it.
MPIOINT Register Multipurpose Input/Output Interrupt Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOLVL [15:0] (default 0x00) The MPIOLVL register controls the output pins and provides the input level status for the input pins. The status of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 (default) sets the output to LOW and a logic 1 sets the output pin to HIGH. The MPIO interrupt will clear upon reading this register.
MPIOLVL Register Multipurpose Output Level Control Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIO3T [15:0] (default 0x00) The MPIO outputs can be tri-stated by the MPIO3T register. A logic 0 (default) sets the output to active level per register MPIOBIT settling, a logic 1 sets the output pin to tri-state.
MPIO3T Register Multipurpose Output 3-state Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOINV [15:0] (default 0x00) The MPIO inputs can be inverted by the MPIOINV register. A logic 0 (default) does not invert the input pin logic. A logic 1 inverts the input logic level.
MPIOINV Register Multipurpose Input Signal Inversion Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
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XR17V354
MPIOSEL [15:0](default 0xFF)
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
The MPIOSEL register defines the MPIOs as either an input or output. A logic 1 (default) defines the pin for input and a logic 0 for output.
MPIOSEL Register Multipurpose Input/Output Selection Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOOD [15:0] (default 0x00) The MPIO outputs can behave as an open-drain output by the MPIOOD register. When the MPIOOD register is a logic 0 (default), the MPIO is not an open-drain output. A logic 1 enables the MPIO as an open-drain output. This register has no effect, when the MPIO is an input.
M P IO O D R eg ister M ultipurpose O pen-D rain O utput E nable B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
M PIO 7 M P IO 6 M P IO 5 M P IO 4 M P IO 3 M P IO 2 M P IO 1 M P IO 0
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PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
2.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data register for each UART channel as shown in Table 4 set to ease programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it increases the data transfer rate on the PCI bus. Additionally, a special register location provides receive data byte with its associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates data unloading with the error flags without having to read the LSR register separately. Furthermore, the XR17V354 supports PCI burst mode for read/write operation of up to 256 bytes of data. The second method is through each UART channel's transmit holding register (THR) and receive holding register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format. The software driver must separately read the LSR content for the associated error flags before reading the data byte. 2.1 FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT The XR17V354 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory location (apart from the individual channel's register set) where the RX and the TX FIFO can be read from/ written to, as shown in Table 4. The following is an extract from the table showing the memory locations that support burst transactions: Channel N: (for channels 0 through 3) where M = 4N + 1. RX FIFO TX FIFO RX FIFO + status Channel 2: RX FIFO TX FIFO RX FIFO + status 2.1.1 : : : 0x0900 - 0x09FF (256 bytes) 0x0900 - 0x09FF (256 bytes) 0x0A00 - 0x0BFF (256 bytes data + 256 bytes status) : : : 0xM00 - 0xMFF (256 bytes) 0xM00 - 0xMFF (256 bytes) 0x(M+1)0 - 0x(M+2)FF (256 bytes data + 256 bytes status)
For example, the locations for channel 2 are:
Normal Rx FIFO Data Unloading at locations 0x100, 0x500, 0x900 and 0xD00
The RX FIFO data (up to the maximum 256 bytes) can be read out in a single burst 32-bit read operation (maximum 16 DWORD reads) at memory locations 0x100 (channel 0), 0x500 (channel 1), 0x900 (channel 2) and 0x0D00 (channel 3). This operation is at least 16 times faster than reading the data in 256 separate 8-bit memory reads of RHR register (0x000 for channel 0, 0x400 for channel 1, 0x800 for channel 2 and 0x0C00 for channel 3).
READ RX FIFO, WITH NO ERRORS Read n+0 to n+3 Read n+4 to n+7 Etc.
BYTE 3 FIFO Data n+3 FIFO Data n+7
BYTE 2 FIFO Data n+2 FIFO Data n+6
BYTE 1 FIFO Data n+1 FIFO Data n+5
BYTE 0 FIFO Data n+0 FIFO Data n+4
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XR17V354
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
Channel 0 to 3 Receive Data in 32-bit alignment through the Configuration Register Address 0x0100, 0x0500, 0x0900 and 0x0D00 Receive Data Byte n+3
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+2
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+1
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus Data Bit-31
PCI Bus Data Bit-0
2.1.2
Special Rx FIFO Data Unloading at locations 0x0200, 0x0600, 0x0A00 and 0x0E00
The XR17V354 also provides the same RX FIFO data along with the LSR status information of each byte sideby-side, at locations 0x0200 (channel 0), 0x0600 (channel 1), 0x0A00 (channel 2) and 0x0E00 (channel 3). The entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD reads. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following tables show this clearly.
WITH LSR
READ RX FIFO, ERRORS
BYTE 3 FIFO Data n+1 FIFO Data n+3
BYTE 2 LSR n+1 LSR n+3
BYTE 1 FIFO Data n+0 FIFO Data n+2
BYTE 0 LSR n+0 LSR n+2
Read n+0 to n+1 Read n+2 to n+3 Etc
Channel 0 to 3 Receive Data with Line Status Register in 32-bit alignment through the Configuration Register Address 0x0200, 0x0600, 0x0A00 and 0x0E00 Receive Data Byte n+1
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+1
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+0
B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus Data Bit-31
PCI Bus Data Bit-0
2.1.3
Tx FIFO Data Loading at locations 0x100, 0x500, 0x900 and 0xD00
The TX FIFO data (up to the maximum 256 bytes) can be loaded in a single burst 32-bit write operation (maximum 16 DWORD writes) at memory locations 0x0100 (channel 0), 0x0500 (channel 1), 0x0900 (channel 2) and 0x0D00 (channel 3).
WRITE TX FIFO Write n+0 to n+3 Write n+4 to n+7 Etc.
BYTE 3 FIFO Data n+3 FIFO Data n+7
BYTE 2 FIFO Data n+2 FIFO Data n+6
BYTE 1 FIFO Data n+1 FIFO Data n+5
BYTE 0 FIFO Data n+0 FIFO Data n+4
30
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
Channel 0 to 3 Transmit Data in 32-bit alignment through the Configuration Register Address 0x0100, 0x0500, 0x0900 and 0x0D00 Transmit Data Byte n+3
B7 B6 B5 B4 B3 B2 B1 B0
Transmit Data Byte n+2
B7 B6 B5 B4 B3 B2 B1 B0
Transmit Data Byte n+1
B7 B6 B5 B4 B3 B2 B1 B0
Transmit Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus Data Bit-31
PCI Bus Data Bit-0
2.2
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-BIT FORMAT
The THR and RHR register address for channel 0 to channel 3 is shown in Table 10 below. The THR and RHR for each channel 0 to 3 are located sequentially at address 0x0000, 0x0200, 0x0400 and 0x0600. Transmit data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus operation can only write or read in bytes. TABLE 10: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH3 (16C550 Compatible) CH0 0x0000 Read THR CH0 0x0000 Write RHR CH1 0x4000 Read THR CH1 0x4000 Write RHR CH2 0x8000 Read THR CH2 0x8000 Write RHR CH3 0xC000 Read THR CH3 0xC000 Write RHR Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0
31
XR17V354
3.0 UART
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
There are 4 UARTs channel [3:0] in the V354. Each has its own 256-byte of transmit and receive FIFO, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel data rate setting. Eight additional registers per UART were added for the EXAR enhanced features. 3.1 Programmable Baud Rate Generator with Fractional Divisor Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The prescaler is controlled by a software bit in the MCR register. The MCR register bit [7] sets the prescaler to divide the internal 125MHz clock (master) or 62.5MHz clock (slave) by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to 1 (DLL = 0x01, DLM = 0x00, DLD = 0x00). The DLL and DLM registers provide the integer part of the divisor and the DLD register provides the fractional part of the divisor. Only the four lower bits of the DLD are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 11 shows the divisor for some standard and non-standard data rates when using the internal 125MHz clock at 16X clock rate. Table 12 shows the divisor for some standard and non-standard data rates when using the internal 62.5MHz clock at 16X clock rate. If the pre-scaler is used (MCR bit [7] = 1), the output data rate will be 4 times less than that shown in Table 11 and Table 12. At 8X sampling rate, these data rates would double. At 4X sampling rate, these data rates would quadruple. Also, when using 8X or 4X sampling mode, note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is an odd number. For data rates not listed in Table 11, the divisor value can be calculated with the following equation(s):
Required Divisor (decimal) = (125MHz or 62.5MHz clock frequency / prescaler) / (serial data rate x 16), WITH 8XMODE =0 AND 4XMODE = 0 Required Divisor (decimal) = (125MHz or 62.5MHz clock frequency / prescaler / (serial data rate x 8), WITH 8XMODE = 1 AND 4XMODE = 0 Required Divisor (decimal) = (125MHz or 62.5MHz clock frequency / prescaler / (serial data rate x 4), WITH 8XMODE = 0 AND 4XMODE = 1
The closest divisor that is obtainable in the V354 can be calculated using the following formula: ROUND( (Required Divisor - TRUNC (Required Divisor) )*16)/16 + TRUNC (Required Divisor), where DLM = TRUNC( Required Divisor) >> 8 DLL = TRUNC (Required Divisor) & 0xFF DLD = ROUND ( (Required Divisor-TRUNC(Required Divisor) )*16) In the formulas above, please note that: TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5. ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
32
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
FIGURE 9. BAUD RATE GENERATOR
To Other Channels
DLL, DLM and DLD Registers 125 MHz Clock (Master) or 62.5 MHz Clock (Slave) Prescaler Divide by 1 MCR Bit-7=0 (default) Fractional Baud Rate Generator Logic MCR Bit-7=1 16X, 8X or 4X Sampling Rate Clock to Transmitter and Receiver
Prescaler Divide by 4
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XR17V354
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
TABLE 11: TYPICAL DATA RATES WITH INTERNAL 125MHZ CLOCK AT 16X SAMPLING (MASTER MODE)
REQUIRED OUTPUT DATA RATE 2400 4800 9600 10000 19200 25000 28800 38400 50000 57600 75000 100000 115200 153600 200000 225000 230400 250000 300000 400000 460800 500000 576000 750000 921600 1000000 1152000 DIVISOR FOR 16x Clock (Decimal) 3255.21 1627.60 813.80 781.25 406.90 312.5 271.27 203.45 156.25 135.63 104.17 78.125 67.82 50.86 39.06 34.72 33.91 31.25 26.04 19.53 16.95 15.625 13.56 10.42 8.48 7.81 6.78 DIVISOR OBTAINABLE IN V354 3255 3/16 1627 9/16 813 12/16 781 4/16 406 14/16 312 8/16 271 4/16 203 7/16 156 4/16 135 10/16 104 2/16 78 2/16 67 13/16 50 13/16 39 1/16 34 11/16 33 14/16 31 4/16 26 19 8/16 16 15/16 15 10/16 13 9/16 10 6/16 8 7/16 7 13/16 6 12/16 DLM PROGRAM VALUE (HEX) 0C 06 03 03 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DLL PROGRAM VALUE (HEX) B7 5B 2D 0D 96 38 0F CB 9C 87 68 4E 43 32 27 22 21 1F 1A 13 10 0F 0D 0A 08 07 06 DLD PROGRAM VALUE (HEX)) 3 9 C 4 E 8 4 7 4 A 2 2 D D 1 B E 4 0 8 F A 9 6 7 D C DATA ERROR RATE (%) 0 0 0.01 0 0.01 0 0.01 0.01 0 0.01 0.04 0 0.01 0.10 0 0.10 0.10 0 0.16 0.16 0.10 0 0.01 0.40 0.47 0 0.47
34
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
TABLE 12: TYPICAL DATA RATES WITH 62.5MHZ CLOCK AT 16X SAMPLING (SLAVE MODE)
REQUIRED OUTPUT DATA RATE 2400 4800 9600 10000 19200 25000 28800 38400 50000 57600 75000 100000 115200 153600 200000 225000 230400 250000 300000 400000 460800 500000 576000 750000 921600 1000000 1152000 DIVISOR FOR 16x Clock (Decimal) 1627.60 813.80 406.90 390.63 203.45 156.25 135.63 101.73 78.13 67.82 52.08 39.06 33.91 25.43 19.53 17.36 16.95 15.63 13.02 9.77 8.48 7.81 6.78 5.21 4.24 3.91 3.39 DIVISOR OBTAINABLE IN V354 1627 9/16 813 12/16 406 14/16 390 10/16 203 7/16 156 4/16 135 10/16 101 11/16 78 2/16 67 13/16 52 1/16 39 1/16 33 14/16 25 6/16 19 8/16 17 5/16 16 15/16 15 10/16 13 0/16 9 12/16 8 7/16 7 13/16 6 12/16 5 3/16 4 3/16 3 14/16 3 6/16 DLM PROGRAM VALUE (HEX) 06 03 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DLL PROGRAM VALUE (HEX) 5B 2D 96 86 CB 9C 87 65 4E 43 34 27 21 19 13 11 10 0F 0D 09 08 07 06 05 04 03 03 DLD PROGRAM VALUE (HEX)) 9 C E A 7 4 A B 2 D 1 1 D 6 8 5 F A 0 C 7 D C 3 3 E 6 DATA ERROR RATE (%) 0 0 0.01 0 0.01 0 0.01 0.04 0 0.01 0.04 0 0.10 0.22 0.16 0.28 0.10 0 0.16 0.16 0.47 0 0.47 0.40 1.22 0.81 0.47
35
XR17V354
3.2
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Automatic hardware or RTS/DTR and CTS/DSR flow control is used to prevent data overrun to the local receiver FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request remote unit to suspend/restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart local transmitter. The auto RTS/DTR and auto CTS/DSR flow control features are individually selected to fit specific application requirement and enabled through EFR bit[7:6] and MCR bit [2] for either RTS/CTS or DTR/DSR control signals. The auto RTS/DTR function must be started by asserting RTS/DTR# output pin (MCR bit [0] or bit [1] to logic 1) after it is enabled. Figure 10 below explains how it works. Two interrupts associated with RTS/DTR and CTS/DSR flow control have been added to give indication when RTS/DTR# pin or CTS/DSR# pin is de-asserted during operation. The RTS/DTR and CTS/DSR interrupts must be first enabled by EFR bit [4], and then enabled individually by IER bits [7:6], and chosen with MCR bit [2]. Automatic hardware flow control is selected by setting bits [7 (CTS): 6 (RTS)] of the EFR register to logic 1. If CTS# pin transitions from LOW to HIGH indicating a flow control request, ISR bit [5] will be set to logic 1, (if enabled via IER bit [7:6]), and the UART will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input returns to LOW, indicating more data may be sent.
36
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
FIGURE 10. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION
Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor RXA TXB Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level
RTSA# TXA
CTSB# RXB
CTSA# Assert RTS# to Begin Transmission 1 ON 2 7 ON 3 8 OFF
RTSB#
RTSA# CTSB# TXB
OFF
10 11
ON ON
Data Starts 4 RXA FIFO INTA (RXA FIFO Interrupt) Receive Data RX FIFO Trigger Level 5
6
Suspend
Restart 9
RTS High Threshold
RTS Low Threshold
12
RX FIFO Trigger Level
RTSCTS1
The local UART (UARTA) starts data transfer by asserting -RTSA# (1). RTSA# is normally connected to CTSB# (2) of remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO (4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows (7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB# and CTSA# controlling the data flow.
37
XR17V354
3.3 Infrared Mode
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
Each UART in the V354 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.1. The input pin ENIR conveniently activates all 4 UART channels to start up in the infrared mode. This global control pin enables the MCR bit [6] function in every UART channel register. After power up or a reset, the software can overwrite MCR bit [6] if so desired. ENIR and MCR bit [6] also disable its receiver while the transmitter is sending data. This prevents the echoed data from going to the receiver. The global activation ENIR pin prevents the infrared emitter from turning on and drawing large amount of current while the system is starting up. When the infrared feature is enabled, the transmit data outputs, TX[3:0], would idle LOW. Likewise, the RX [3:0] inputs assume a LOW idle level. The infrared encoder sends out a 3/16 of a bit wide pulse for each "0" bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See Figure 11 below. Typical max data rate for the infrared encoder with a 3/16 of a bit wide pulse is 115.2 kbps. For data rates above 115.2 kbps and up to1.152 Mbps, Fast IR mode can be enabled via DLD bit-4 for a 1/4 of bit wide pulse. For exact 3/16 or 1/4 of a bit wide pulse, the 16X sampling rate should be used and DLD[3:0] = '0000'. The IR pulse width can vary if DLD[3:0] is not '0000'. The infrared decoder receives the input pulse from the infrared sensing diode on RX pin. Each time the decoder senses a light pulse, it returns a "0" to the data bit stream. The RX input signal may be inverted prior delivered to the input of the decoder via internal register setting. This option supports active LOW instead of normal active HIGH pulse from some infrared modules on the market. FIGURE 11. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character Start Data Bits 1 0 1 0 0 1 1 0 Stop 1 1/2 Bit Time
IrEncoder-1
TX Data
0
Transmit IR Pulse (TX Pin) Bit Time 3/16 or 1/4 Bit Time
Receive IR Pulse (RX pin)
Bit Time 1/16 Clock Delay
RX Data
0 Start
1
0
1
0
0
1
1
0
1 Stop
IRdecoder-1
Data Bits Character
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REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
3.4
Internal Loopback
Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit [4] to a logic 1. All regular UART functions operate normally. Figure 12 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX pin is held at HIGH or mark condition while RTS# and DTR# are de-asserted. The CTS#, DSR#, CD# and RI# inputs are ignored. FIGURE 12. INTERNAL LOOP BACK
VCC
Transmit Shift Register
MCR bit-4=1
TX [3:0]
Internal Bus Lines and Control Signals
Receive Shift Register
VCC
RX [3:0]
RTS# [3:0]
RTS#
Modem / General Purpose Control Logic
CTS# VCC DTR#
CTS# [3:0] DTR# [3:0]
DSR# OP1# RI# OP2# CD#
DSR# [3:0] RI# [3:0] CD# [3:0]
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XR17V354
3.5
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART UART CHANNEL CONFIGURATION REGISTERS
Address lines A0 to A3 select the 16 registers in each channel. The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 addresses. TABLE 13: UART CHANNEL CONFIGURATION REGISTERS
ADDRESS A3 A2 A1 A0 16550 COMPATIBLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 00 00 01 10 01 10 11 00 01 10 11 RHR - Receive Holding Register THR - Transmit Holding Register DLL - Divisor LSB DLM - Divisor MSB DLD - Divisor Fractional IER - Interrupt Enable Register ISR - Interrupt Status Register FCR - FIFO Control Register LCR - Line Control Register MCR - Modem Control Register LSR - Line Status Register MSR - Modem Status Register - Auto RS485 Delay SPR - Scratch Pad Register ENHANCED REGISTER 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 00 01 10 11 00 01 10 11 FCTR - Feature Control Register EFR - Enhanced Function Register TXCNT - Transmit FIFO Level Counter TXTRG - Transmit FIFO Trigger Level RXCNT - Receive FIFO Level Counter RXTRG - Receive FIFO Trigger Level Xoff-1 - Xoff Character 1 Xchar Xoff-2 - Xoff Character 2 Xon-1 - Xon Character 1 Xon-2 - Xon Character 2 Read/Write Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Write-only Write-only Write-only Xon,Xoff Rcvd. Flags Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Read-only Write-only Read/Write EFR bit-4 = 1 LCR[7] = 0 LCR[7] = 1 LCR[7] = 1 LCR[7] = 1 LCR[7] = 0 LCR[7] = 0 REGISTER READ/WRITE COMMENTS
40
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
TABLE 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS A3-A0 0000 0000 0000 0001 0010 REG NAME RHR THR DLL DLM DLD READ/ WRITE R W R/W R/W R/W BIT [7] BIT [7] BIT [7] BIT [7] BIT [7] Invert RS485 Polarity 0/ CTS/ DSR# Int. Enable 0010 ISR R FIFOs Enable BIT [6] BIT [6] BIT [6] BIT [6] BIT [6] Multidrop mode 0/ BIT [5] Bit [5] Bit [5] Bit [5] Bit [5] XON/ XOFF parity check 0/ BIT [4] Bit [4] Bit [4] Bit [4] Bit [4] Fast IR mode BIT [3] Bit [3] Bit [3] Bit [3] Bit [3] Bit [3] BIT [2] Bit [2] Bit [2] Bit [2] Bit [2] Bit [2] BIT[1] Bit [1] Bit [1] Bit [1] Bit [1] Bit [1] BIT [0] Bit [0] Bit [0] Bit [0] Bit [0] Bit [0]
COMMENT
LCR[7]=0 LCR[7]=0 LCR[7]=1 LCR[7]=1 LCR[7]=1
0001
IER
R/W
0
RTS/ Xon/ DTR# Xoff/Sp. Int. Char. Int. Enable Enable FIFOs Enable 0/ DeltaFlow Cntl 0/ TX FIFO Trigger 0/ Xoff/special char 0/ TX FIFO Trigger
Modem Status Int. Enable
RX Line Status Int. Enable
TX Empty Int. Enable
RX Data Int. Enable
LCR[7]=0
INT Source Bit [3]
INT Source Bit [2]
INT Source Bit [1]
INT Source Bit [0]
LCR[7]=0
0010
FCR
W
RX FIFO RX FIFO Trigger Trigger
DMA Mode
TX FIFO RX FIFO Reset Reset
FIFOs Enable
LCR[7]=0
0011
LCR
R/W
Divisor Enable 0/ BRG Prescaler
Set TX Break 0/ IR Enable TSR Empty RI RS485 DLY[2] Bit [6] TRG Table Bit [0]
Set Par- Even Parity ity 0/ XonAny Internal Loopback Enable
Parity Stop Bits Enable (OP2)1 (OP1)1
Word Length Bit [1]
Word Length Bit [0]
0100
MCR
R/W
TX char RTS/ ImmediDTR ate Flow Sel
RTS# DTR# Pin Con- Pin Control trol
0101
LSR
R
RX FIFO Error CD RS485 DLY[3] Bit [7] TRG Table Bit [1]
THR Empty DSR RS485 DLY[1] Bit [5] Auto RS485 Enable
RX Break
RX RX ParRX RX Data Framing ity Error Overrun Ready Error Delta CD# Disable TX Bit [3] RTS/ DTR Hyst Bit [3] Delta RI# Delta DSR# Delta CTS#
0110
MSR MSR
R W R/W R/W
CTS RS485 DLY[0] Bit [4] Invert IR RX Input
Disable Disable Disable RX TX mode RX mode Bit [2] RTS/ DTR Hyst Bit [2] Bit [1] RTS/ DTR Hyst Bit [1] Bit [0] RTS/ DTR Hyst Bit [0] User Data
0111 1000
SPR FCTR
41
XR17V354
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
TABLE 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS A3-A0 1001 REG NAME EFR READ/ WRITE R/W BIT [7] Auto CTS/ DSR Enable BIT [6] Auto RTS/ DTR Enable BIT [5] Special Char Select BIT [4] Enable IER [7:5], ISR [5:4], FCR[5:4], MCR[7:5], MSR Bit [4] Bit [4] Bit [4] Bit [4] 0 Bit [4] Bit [4] Bit [4] Bit [4] BIT [3] Software Flow Cntl Bit [3] BIT [2] Software Flow Cntl Bit [2] BIT[1] Software Flow Cntl Bit [1] BIT [0] Software Flow Cntl Bit [0]
COMMENT
1010 1010 1011 1011 1100 1100 1101 1110 1111 NOTE:
TXCNT TXTRG RXCNT RXTRG XCHAR XOFF1 XOFF2 XON1 XON2
R W R W R W W W W
Bit [7] Bit [7] Bit [7] Bit [7] 0 Bit [7] Bit [7] Bit [7] Bit [7]
Bit [6] Bit [6] Bit [6] Bit [6] 0 Bit [6] Bit [6] Bit [6] Bit [6]
Bit [5] Bit [5] Bit [5] Bit [5] 0 Bit [5] Bit [5] Bit [5] Bit [5]
Bit [3] Bit [3] Bit [3] Bit [3]
Bit [2] Bit [2] Bit [2] Bit [2]
Bit [1] Bit [1] Bit [1] Bit [1]
Bit [0] Bit [0] Bit [0] Bit [0] Self clear after read
TX Xon TX Xoff Xon Det. Xoff Det. Indicator Indicator Indicator Indicator Bit [3] Bit [3] Bit [3] Bit [3] Bit-2 Bit-2 Bit-2 Bit-2 Bit [1] Bit [1] Bit [1] Bit [1] Bit [0] Bit [0] Bit [0] Bit [0]
MCR bits [3:2] (OP1 and OP2 outputs) are not available in the XR17V354. They are present for 16C550 compatibility during Internal loopback, see Figure 12.
3.6
Transmitter
The transmitter section comprises of a 256 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an 8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte from the FIFO when the FIFO is enabled by FCR bit [0]. TSR shifts out every data bit with the 16X or 8X internal clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits, inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are reported in the Line Status Register (LSR bit [6:5]). 3.6.1 Transmit Holding Register (THR) The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (bit [0]) becomes first data bit to go out. The THR is also the input register to the transmit FIFO of 256 bytes when FIFO operation is enabled by FCR bit[0]. A THR empty interrupt can be generated when it is enabled in IER bit [1]. 3.6.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit [5]) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit [1]) when it is enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely empty.
42
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
FIGURE 13. TRANSMITTER OPERATION IN NON-FIFO MODE
D a ta B y te
T r a n s m it H o ld i n g R e g is te r (T H R )
T H R In te r r u p t ( IS R b it- 1 ) E n a b le d b y I E R b it - 1
16X or 8X or 4X C lo c k T r a n s m it S h if t R e g is t e r ( T S R )
M S B
L S B
3.6.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 256 bytes of transmit data. The THR empty flag (LSR bit [5]) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit [1]) when the amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty interrupt is enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely empty. Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit [5]=1) the source of the transmit empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not changed until the last stop bit of the last character is shifted out. 3.6.4 Auto RS485 Operation The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR bit [5]. It de-asserts RTS# or DTR# after a specified delay indicated in MSR[7:4] following the last stop bit of the last character that has been transmitted. This helps in turning around the transceiver to receive the remote station's response. The delay optimizes the time needed for the last transmission to reach the farthest station on a long cable network before switching off the line driver. This delay prevents undesirable line signal disturbance that causes signal degradation. It also changes the transmitter empty interrupt to TSR empty instead of THR empty. FIGURE 14. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit Data Byte
Transmit FIFO (256-Byte)
Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control 16X or 8X or 4X Clock
THR Interrupt (ISR bit-1) falls below Programmed Trigger Level (TXTRG) and then when becomes empty. FIFO is Enabled by FCR bit-0=1
Transmit Data Shift Register (TSR)
Auto CTS Flow Control (CTS# pin)
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XR17V354
3.7 Receiver
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X, 8X or 4X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X, 8X or 4X clock rate. After 8 or 4 or 2 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits [4:1]. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word lengths as defined by LCR bits [1:0] plus 12 bits time. The RHR interrupt is enabled by IER bit [0]. 3.7.1 Receiver Operation in non-FIFO Mode
FIGURE 15. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X or 4X Clock
Receive Data Shift Register (RSR)
Data Bit Validation
Receive Data Characters
Receive Data Byte and Errors
Error Flags in LSR bits 4:2
Receive Data Holding Register (RHR)
RHR Interrupt (ISR bit-2)
44
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART Receiver Operation with FIFO
3.7.2
FIGURE 16. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
16X or 8X or 4X Clock
Receive Data Shift Register (RSR)
Data Bit Validation
Receive Data Characters
256 bytes by 11-bits wide FIFO
Example: - FIFO trigger level set at 128 bytes - RTS/DTR hyasteresis set at +/-32 chars. Data falls to 96 Error Flags (256-sets)
RTS#/DTR# re-asserts when data falls below the trigger level to restart remote transmitter. Enable by EFR bit-6=1, MCR bit-2. RHR Interrupt (ISR bit-2) is programmed at FIFO trigger level (RXTRG). FIFO is Enable by FCR bit-0=1 RTS#/DTR# de-asserts when data fills above the trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-2.
Receive Data FIFO (256-byte)
FIFO Trigger=128
Data fills to 160 Error Flags in LSR bits 4:2
Receive Data Byte and Errors
Receive Data
3.7.3
Normal Multidrop (9-bit) Mode
Normal multidrop mode is enabled when DLD[6] = 1 and EFR[5] = 0 (Special Character Detect disabled). The receiver is set to Force Parity 0 (LCR[5:3] = '111') in order to detect address bytes. With the receiver initially disabled (MSR[2] = 1), it ignores all the data bytes (parity bit = 0) until an address byte is received (parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate an LSR interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the receiver if the address matches its slave address, otherwise, it does not enable the receiver. If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received, it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave address, it does not have to do anything. If the address does not match its slave address, then the receiver should be disabled. 3.7.4 Auto Address Detection Mode Auto address detection mode is enabled when DLD[6] = 1 and EFR bit-5 = 1 (Special Character Detect enabled). The receiver is set to Force Parity 0 (LCR[5:3] = '111') in order to detect address bytes. The desired slave address will need to be written into the XOFF2 register. The receiver will monitor all incoming address bytes and compare with the programmed character in the XOFF2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the XOFF2 register, the receiver will discard the data. Upon receiving an address byte that matches the XOFF2 character, the receiver will be automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also generates an LSR interrupt. The receiver will then receive the subsequent data. If another address byte is received and this address does not match the programmed XOFF2 character, then the receiver will automatically be disabled and all subsequent data is ignored until there is another address byte match with XOFF2.
45
XR17V354
4.0 UART CONFIGURATION REGISTERS 4.1 4.2 4.3
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART Receive Holding Register (RHR) - Read only Transmit Holding Register (THR) - Write only Baud Rate Generator Divisors (DLM, DLL and DLD)
SEE"RECEIVER" ON PAGE 44. SEE"TRANSMITTER" ON PAGE 42. DLM[7:0], DLL[7:0] and DLD[3:0] The Baud Rate Generator (BRG) generates the data rate for the transmitter and receiver. The rate is programmed through registers DLM, DLL and DLD which are only accessible when LCR bit [7] is set to logic 1. Refer to "Section 3.1, Programmable Baud Rate Generator with Fractional Divisor" on page 32 for more details. DLD[7]: RS-485 Polarity
* Logic 0 = The Auto RS-485 Half-duplex direction control pin will be HIGH for TX and LOW for RX. * Logic 1 = The Auto RS-485 Half-duplex direction control pin will be LOW for TX and HIGH for RX.
DLD[6]: Multi-drop Mode
* Logic 0 = Normal mode. * Logic 1 = Enable Multi-drop mode.
DLD[5]: XON/XOFF Parity Check
* Logic 0 = XON/XOFF characters are valid flow control characters even if they have parity errors. * Logic 1 = XON/XOFF characters are not valid flow control characters if they have parity errors.
DLD[4]: Fast IR Mode
* Logic 0 = If IR mode is enabled, IR pulsewidth will be 3/16th of bit time. * Logic 1 = If IR mode is enabled, IR pulsewidth will be 1/4th of bit time.
4.4 Interrupt Enable Register (IER) - Read/Write The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) and also encoded in INT (INT0-INT3) register in the Device Configuration Registers. 4.4.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR bit [0] = logic 1) and receive interrupts (IER bit [0] = logic 1) are enabled, the RHR interrupts (see ISR bits [4:3]) status will reflect the following: A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C. The receive data ready bit (LSR bit [0]) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty.
46
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART IER versus Receive/Transmit FIFO Polled Mode Operation
4.4.2
When FCR bit [0] equals a logic 1 for FIFO enable; resetting IER bits [3:0] enables the XR16V354 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either can be used in the polled mode by selecting respective transmit or receive control bit(s). A. LSR BIT-0 indicates there is data in RHR (non-FIFO mode) or RX FIFO (FIFO mode). B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid. C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any. D. LSR BIT-5 indicates THR (non-FIFO mode) or TX FIFO (FIFO mode) is empty. E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty. F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO. IER[7]: CTS# Input Interrupt Enable (requires EFR bit [4]=1)
* Logic 0 = Disable the CTS# interrupt (default). * Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
LOW to HIGH. IER[6]: RTS# Output Interrupt Enable (requires EFR bit [4]=1)
* Logic 0 = Disable the RTS# interrupt (default). * Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when RTS# pin makes a transition from
LOW to HIGH. IER[5]: Xoff Interrupt Enable (requires EFR bit [4]=1)
* Logic 0 = Disable the software flow control, receive Xoff interrupt (default). * Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details. IER[4]: Reserved IER[3]: Modem Status Interrupt Enable The Modem Status Register interrupt is issued whenever any of the delta bits of the MSR register (bits [3:0]) is set.
* Logic 0 = Disable the modem status register interrupt (default). * Logic 1 = Enable the modem status register interrupt.
IER[2]: Receive Line Status Interrupt Enable An Overrun error, Framing error, Parity error or detection of a Break character will result in an LSR interrupt. The V354 will issue an LSR interrupt immediately after receiving a character with an error. It will again re-issue the interrupt (if the first one has been cleared by reading the LSR register) when the character with the error is on the top of the FIFO, meaning the next one to be read out of the FIFO. For example, let's consider an incoming data stream of 0x55, 0xAA, etc. and that the character 0xAA has a Parity error associated with it. Let's assume that the character 0x55 has not been read out of the FIFO yet. The V354v354 will issue an interrupt as soon as the stop bit of the character 0xAA is received. The LSR register will have only the FIFO error bit (bit [7]) set and none of the other error bits (bits [4:1]) will be set, since the byte on the top of the FIFO is 0x55 which does not have any errors associated with it. When this byte has been read out, the V354 will issue another LSR interrupt and this time the LSR register will show the Parity bit (bit [2]) set.
* Logic 0 = Disable the receiver line status interrupt (default). * Logic 1 = Enable the receiver line status interrupt.
47
XR17V354
IER[1]: TX Ready Interrupt Enable
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
In non-FIFO mode, a TX interrupt is issued whenever the THR is empty. In the FIFO mode, an interrupt is issued twice: once when the number of bytes in the TX FIFO falls below the programmed trigger level and again when the TX FIFO becomes empty. When autoRS485 mode is enabled (FCTR bit [5] = 1), the second interrupt is delayed until the transmitter (both the TX FIFO and the TX Shift Register) is empty.
* Logic 0= Disable Transmit Ready Interrupt (default). * Logic 1 = Enable Transmit Ready Interrupt.
IER[0]: RX Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode.
* Logic 0 = Disable the receive data ready interrupt (default). * Logic 1 = Enable the receiver data ready interrupt.
4.5 Interrupt Status Register (ISR) - Read Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 15, shows the data values (bit [5:0]) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. 4.5.1 Interrupt Generation:
* LSR is by any of the LSR bits [4:1]. See IER bit [2] description on the previous page. * RXRDY is by RX trigger level. * RXRDY Time-out is by a 4-char plus 12 bits delay timer. * TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control). * MSR is by any of the MSR bits [3:0]. * Receive Xoff/Xon/Special character is by detection of a Xoff, Xon or Special character. * CTS#/DSR# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS/DSR flow
control enabled by EFR bit [7] and selection on MCR bit [2].
* RTS#/DTR# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS/DTR flow
control enabled by EFR bit [6] and selection on MCR bit [2].
* Wake-up indicator is when the UART wakes up from the sleep mode.
4.5.2 Interrupt Clearing:
* LSR interrupt is cleared by a read to the LSR register. * RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. * RXRDY Time-out interrupt is cleared by reading RHR. * TXRDY interrupt is cleared by a read to the ISR register or writing to THR. * MSR interrupt is cleared by a read to the MSR register. * Xoff/Xon interrupt is cleared by reading ISR. * Special character interrupt is cleared by a read to ISR. * RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
48
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HIGH PERFORMANCE QUAD PCI-EXPRESS UART
* Wake-up indicator is cleared by a read to the INT0 register.
]
TABLE 15: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY LEVEL 1 2 3 4 5 6 7 X BIT [5] 0 0 0 0 0 0 1 0 ISR REGISTER STATUS BITS BIT [4] 0 0 0 0 0 1 0 0 BIT [3] 0 0 1 0 0 0 0 0 BIT [2] 1 1 1 0 0 0 0 0 BIT [1] 1 0 0 1 0 0 0 0 BIT [0] 0 0 0 0 0 0 0 1 LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data Time-out) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register) RXRDY (Received Xon/Xoff or Special character) CTS#/DSR#, RTS#/DTR# change of state None (default) SOURCE OF THE INTERRUPT
ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. ISR[5:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 15). See "Section 4.5.1, Interrupt Generation:" on page 48 and "Section 4.5.2, Interrupt Clearing:" on page 48 for details. ISR[0]: Interrupt Status
* Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
* Logic 1 = No interrupt pending. (default condition)
4.6 FIFO Control Register (FCR) - Write Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) The FCTR bits [5:4] are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 16 shows the complete selections. Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side. FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit [4]=1) (logic 0 = default, TX trigger level = 1) The FCTR bits [7:6] are associated with these 2 bits by selecting one of the four tables. The 4 user selectable trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the trigger level on last re-load. Table 16 below shows the selections.
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This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy software compatibility.
* Logic 0 = Set DMA to mode 0 (default). * Logic 1 = Set DMA to mode 1.
FCR[2]: TX FIFO Reset This bit is only active when FCR bit [0] is active.
* Logic 0= No transmit FIFO reset (default). * Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[1]: RX FIFO Reset This bit is only active when FCR bit [0] is active.
* Logic 0 = No receive FIFO reset (default). * Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[0]: TX and RX FIFO Enable
* Logic 0 = Disable the transmit and receive FIFO (default). * Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed. TABLE 16: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRIGGER TABLE Table-A FCTR FCTR FCR FCR FCR FCR RECEIVE BIT [7] BIT [6] BIT [7] BIT [6] BIT [5] BIT [4] TRIGGER LEVEL 0 0 0 0 1 1 Table-B 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 16 24 28 0 0 1 (default) 4 8 14 16 8 24 30 TRANSMIT TRIGGER LEVEL 1 (default) COMPATIBILITY 16C550, 16C2550, 16C2552, 16C554, 16C580, 16L580
16C650A, 16L651
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TRIGGER TABLE Table-C
FCTR FCTR FCR FCR FCR FCR RECEIVE BIT [7] BIT [6] BIT [7] BIT [6] BIT [5] BIT [4] TRIGGER LEVEL 1 0 0 0 1 1 0 0 1 1 0 1 0 1 X X X 0 1 0 1 8 16 56 60
TRANSMIT TRIGGER LEVEL 8 16 32 56
COMPATIBILITY 16C654
Table-D
1
1
X
Programmable Programmable 16L2752, 16L2750, via RXTRG via TXTRG 16C2852, 16C850, 16C854, 16C864 register register
4.7
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL, DLM, DLD) enable.
* Logic 0 = Data registers are selected (default). * Logic 1 = Divisor latch registers (DLL, DLM and DLD) are selected.
LCR[6]: Transmit Break Enable When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a "space", LOW, state). This condition remains until disabled by setting LCR bit [6] to a logic 0.
* Logic 0 = No TX break condition. (default) * Logic 1 = Forces the transmitter output (TX) to a "space", LOW, for alerting the remote receiver of a line
break condition. LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR bit [5] selects the forced parity format.
* LCR bit [5] = logic 0, parity is not forced (default). * LCR bit [5] = logic 1 and LCR bit [4] = logic 0, parity bit is forced to a logical 1for the transmit and receive
data.
* LCR bit [5] = logic 1 and LCR bit [4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
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LCR BIT [5] X 0 0 1 1 LCR BIT [4] X 0 1 0 1 LCR BIT [3] 0 1 1 1 1 PARITY SELECTION No parity Odd parity Even parity Force parity to mark, "1" Forced parity to space, "0"
LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit [3] set to a logic 1, LCR bit [4] selects the even or odd parity format.
* Logic 0 = ODD Parity is generated by forcing an odd number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format (default).
* Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1's in the transmitted character.
The receiver must be programmed to check the same format. LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 17 above for parity selection summary.
* Logic 0 = No parity. * Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received. LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT [2] 0 1 1
WORD
LENGTH
STOP BIT LENGTH (BIT TIME(S)) 1 (default) 1-1/2 2
5,6,7,8 5 6,7,8
LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received.
BIT [1] 0 0 1 1
BIT [0] 0 1 0 1
WORD LENGTH 5 (default) 6 7 8
4.8
Modem Control Register (MCR) - Read/Write
The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs.
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MCR[7]: Clock Prescaler Select (requires EFR bit [4]=1)
* Logic 0 = Divide by one. The internal 125MHz clock (master) or 62.5MHz clock (slave) is fed directly to the
Programmable Baud Rate Generator without further modification, i.e., divide by one (default).
* Logic 1 = Divide by four. The prescaler divides the internal 125MHz clock (master) or 62.5MHz clock (slave)
by 4 and feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth. MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit [4]=1) The state of this bit depends on the sampled logic level of pin ENIR during power up, following a hardware reset (rising edge of RST# input). Afterward user can override this bit for desired operation.
* Logic 0 = Enable the standard modem receive and transmit character interface. * Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/
input are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode the infrared TX output will be a LOW during idle data conditions. FCTR bit [4] may be selected to invert the RX input signal level going to the decoder for infrared modules that provide rather an inverted output. For exact 3/16 or 1/4 bit wide pulse, the 16X sampling rate must be used and DLD[3:0] = '0000'. If DLD[3:0] is not '0000', the pulse width can vary. MCR[5]: Xon-Any Enable (requires EFR bit [4]=1)
* Logic 0 = Disable Xon-Any function (default). * Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data
transmission. MCR[4]: Internal Loopback Enable
* Logic 1 = Disable loopback mode (default). * Logic 1 = Enable local loopback mode, see loopback section and Figure 12.
MCR[3]: Send Char Immediate (OP2 in Local Loopback Mode) This bit is used to transmit a character immediately irrespective of the bytes currently in the transmit FIFO. The data byte must be loaded into the transmit holding register (THR) immediately following the write to this bit (to set it to a '1'). In other words, no other register must be accessed between setting this bit and writing to the THR. The loaded byte will be transmitted ahead of all the bytes in the TX FIFO, immediately after the character currently being shifted out of the transmit shift register is sent out. The existing line parameters (parity, stop bits) will be used when composing the character. This bit is self clearing, therefore, must be set before sending a custom character each time. Please note that the Transmitter must be enabled for this function (MSR[3] = 0). Also, if software flow control is enabled, the software flow control characters (Xon, Xoff) have higher priority and will get shifted out before the custom byte is transmitted.
* Logic 0 = Send Char Immediate disabled (default). * Logic 1 = Send Char Immediate enabled.
In Local Loopback Mode (MCR[4] = 1), this bit acts as the legacy OP2 output and controls the CD bit in the MSR register as shown in Figure 12. Please make sure that this bit is a '0' when exiting the Local Loopback Mode.
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DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by EFR bit [6]. DTR# selection is associated with DSR# and RTS# is with CTS#.
* Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control. * Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control.
In Local Loopback mode (MCR[4] = 1), this bit acts as the legacy OP1 output and controls the RI bit in the MSR register, as shown in Figure 12. MCR[1]: RTS# Output The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit [6] and MCR bit [2]=0. If the modem interface is not used, this output may be used for general purpose.
* Logic 0 = Force RTS# output to a HIGH (default). * Logic 1= Force RTS# output to LOW.
MCR[0]: DTR# Output The DTR# pin may be used for automatic hardware flow control enabled by EFR bit [6] and MCR bit [2]=1. If the modem interface is not used, this output may be used for general purpose.
* Logic 0 = Force DTR# output to a HIGH (default). * Logic 1 = Force DTR# output to a LOW.
4.9 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. If IER bit [2] is set to a logic 1, an LSR interrupt will be generated immediately when any character in the RX FIFO has an error (parity, framing, overrun, break). LSR[7]: Receive FIFO Data Error Flag
* Logic 0 = No FIFO error (default). * Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there are no more errors in the FIFO. LSR[6]: Transmitter Empty Flag This bit is the Transmitter Empty indicator. This bit is set to a logic 1 whenever both the transmit FIFO (or THR, in non-FIFO mode) and the transmit shift register (TSR) are both empty. It is set to logic 0 whenever either the TX FIFO or TSR contains a data character. LSR[5]: Transmit FIFO Empty Flag This bit is the Transmit FIFO Empty indicator. This bit indicates that the transmitter is ready to accept a new character for transmission. This bit is set to a logic HIGH when the last data byte is transferred from the transmit FIFO to the transmit shift register. The bit is reset to logic 0 as soon as a data byte is loaded into the transmit FIFO. In the non-FIFO mode this bit is set when the transmit holding register (THR) is empty; it is cleared when at a byte is written to the THR. LSR[4]: Receive Break Flag
* Logic 0 = No break condition (default). * Logic 1 = The receiver received a break signal (RX was LOW for one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, "mark" or HIGH.
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LSR[3]: Receive Data Framing Error Flag
* Logic 0 = No framing error (default). * Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. LSR[2]: Receive Data Parity Error Flag
* Logic 0 = No parity error (default). * Logic 1 = Parity error. The receive character in RHR (top of the FIFO) does not have correct parity
information and is suspect. This error is associated with the character available for reading in RHR. LSR[1]: Receiver Overrun Flag
* Logic 0 = No overrun error (default). * Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. LSR[0]: Receive Data Ready Indicator
* Logic 0 = No data in receive holding register or FIFO (default). * Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
4.10 Modem Status Register (MSR) - Read Only This register provides the current state of the modem interface signals, or other peripheral device that the UART is connected. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose inputs/outputs when they are not used with modem signals. MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit [3] in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit [2] in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. MSR[5]: DSR Input Status DSR# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS/DSR bit (EFR bit [6]=1) and RTS/DTR flow control select bit (MCR bit [2]=1). Auto CTS/DSR flow control allows starting and stopping of local data transmissions based on the modem DSR# signal. A HIGH on the DSR# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally MSR bit [5] is the complement of the DSR# input. However in the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. MSR[4]: CTS Input Status CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS/DSR bit (EFR bit [6]=1) and RTS/DTR flow control select bit (MCR bit [2]=0). Auto CTS/DSR flow control allows starting and stopping of local data transmissions based on the modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally MSR bit [4] is the complement of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used.
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MSR[3]: Delta CD# Input Flag
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* Logic 0 = No change on CD# input (default). * Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit [3]). MSR[2]: Delta RI# Input Flag
* Logic 0 = No change on RI# input (default). * Logic 1 = The RI# input has changed from a LOW to a HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit [3]). MSR[1]: Delta DSR# Input Flag
* Logic 0 = No change on DSR# input (default). * Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]). MSR[0]: Delta CTS# Input Flag
* Logic 0 = No change on CTS# input (default). * Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]). 4.11 Modem Status Register (MSR) - Write Only The upper four bits [7:4] of this register set the delay in number of bits time for the auto RS-485 turn around from transmit to receive. MSR [7:4]: Auto RS485 Turn-Around Delay (requires EFR bit [4]=1) When Auto RS485 feature is enabled (FCTR bit [5]=1) and RTS#/DTR# output is connected to the enable input of a RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last transmitted character. This delay controls when to change the state of RTS#/DTR# output. This delay is very useful in long-cable networks. Table 18 shows the selection. The bits are enabled by EFR bit-4.
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TABLE 18: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE
MSR[7] 0 0 0 0 0 9 0 0 1 1 1 1 1 1 1 1 MSR[6] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MSR[5] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MSR[4] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DELAY IN DATA BIT(S) TIME 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSR [3]: Transmitter Disable This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set to a logic 1, the bytes already in the FIFO will not be sent out. Also, any more data loaded into the FIFO will stay in the FIFO and will not be sent out. When this bit is set to a logic 0, the bytes currently in the TX FIFO will be sent out. Please note that setting this bit to a logic 1 stops any character from going out. Also, this bit must be a logic 0 for the Send Char Immediate function (see MCR[3]).
* Logic 0 = Enable Transmitter (default). * Logic 1 = Disable Transmitter.
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This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to a logic 1, the receiver will operate in one of the following ways:
If a character is being received at the time of setting this bit, that character will be correctly received. No more characters will be received. If the receiver is idle at the time of setting this bit, no more characters will be received.
The receiver can be enabled and will start receiving characters by resetting this bit to a logic 0. The receiver will operate in one of the following ways:
If the receiver is idle (RX pin is HIGH) at the time of setting this bit, the next character will be received normally. It is recommended that the receiver be idle when resetting this bit to a logic 0. If the receiver is not idle (RX pin is toggling) at the time of setting this bit, the RX FIFO will be filled with unknown data.
Any data that is in the RX FIFO can be read out at any time whether the receiver is disabled or not.
* Logic 0 = Enable Receiver (default). * Logic 1 = Disable Receiver.
MSR [1]: Transmitter Disable Modes This bit is only applicable when MSR[3] = 1.
* Logic 0 = No xon/xoff software flow control characters will be transmitted when the transmitter is disabled. If
there is a pending xon/xoff character to be sent while the transmitter is disabled, it will be transmitted. No additional xon/xoff characters will be sent.
* Logic 1 = Xon/xoff software flow control characters will be transmitted even though the transmitter is
disabled. MSR[0]: Receiver Disable Modes This is only applicable when MSR[2] = 1.
* Logic 0 = All RX data and xon/xoff flow control characters are ignored. * Logic 1 = All RX data is ignored. Xon/xoff flow control characters are detected and acted upon.
4.12 SCRATCH PAD REGISTER (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. 4.13 FEATURE CONTROL REGISTER (FCTR) - Read/Write This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654. FCTR[7:6]: TX and RX FIFO Trigger Table Select These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550 and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one FIFO level above and one FIFO level below. See in Table 16 for complete selection with FCR bit [5:4] and FCTR bits [7:6], i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will de-assert at 60 and re-assert at 16.
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FCTR[5]: Auto RS485 Enable Auto RS485 half duplex control enable/disable. RTS# or DTR# can be selected as the control output via MCR bit-2. Note that this feature has precedence over the Auto RTS/DTR flow control feature (EFR bit-6). Therefore, the Auto RTS/DTR flow control feature will not have any effect when the Auto RS485 Half-Duplex Direction Control feature is enabled.
* Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
* Logic 1 = Enable Auto RS485 half duplex direction control. RTS#/DTR# output changes from HIGH to LOW
when finished sending the last stop bit of the last character out of the TSR register. It changes from LOW to HIGH when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register (TSR) empty. If software flow control is enabled, the RTS#/DTR# output will not change if the TX FIFO is empty and the RX FIFO level generates an XON or XOFF character to be transmitted. FCTR[4]: Infrared RX Input Logic Select
* Logic 0 = Select RX input as active HIGH encoded IrDA data, normal, (default). * Logic 1 = Select RX input as active LOW encoded IrDA data, inverted.
FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is selected (FCTR bit [7:6] are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger level. After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control. Table 19 below shows the 16 selectable hysteresis levels. TABLE 19: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT [3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FCTR BIT [2] 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 FCTR BIT [1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FCTR BIT [0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RTS/DTR HYSTERESIS (CHARACTERS) 0 +/- 4 +/- 6 +/- 8 +/- 8 +/- 16 +/- 24 +/- 32 +/- 12 +/- 20 +/- 28 +/- 36 +/- 40 +/- 44 +/- 48 +/- 52
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Enhanced features are enabled or disabled using this register. Bits [3:0] provide single or dual consecutive character software flow control selection (see Table 20). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. EFR[7]: Auto CTS Flow Control Enable Automatic CTS or DSR Flow Control.
* Logic 0 = Automatic CTS/DSR flow control is disabled (default). * Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS/DSR# pin de-asserts
(HIGH). Transmission resumes when CTS/DSR# pin is asserted (LOW). The selection for CTS# or DSR# is through MCR bit [2]. EFR[6]: Auto RTS or DTR Flow Control Enable RTS#/DTR# output may be used for hardware flow control by setting EFR bit [6] to logic 1. When Auto RTS/ DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level. RTS/DTR# will reassert (LOW) when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 47). The RTS# or DTR# output must be asserted (LOW) before the auto RTS/DTR can take effect. The selection for RTS# or DTR# is through MCR bit [2]. RTS/DTR# pin will function as a general purpose output when hardware flow control is disabled.
* Logic 0 = Automatic RTS/DTR flow control is disabled (default). * Logic 1 = Enable Automatic RTS/DTR flow control.
EFR[5]: Special Character Detect Enable
* Logic 0 = Special Character Detect Disabled (default). * Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit [4] will be set to indicate detection of the special character. bit [0] corresponds with the LSB bit for the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character interrupt. EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the enhanced functions in IER bits [7:5], ISR bits [5:4], FCR bits [5:4], MCR bits [7:5] and MSR [7:0] bits to be modified. After modifying any enhanced bits, EFR bit [4] can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled.
* Logic 0 = Disable write access to the enhanced function bits: IER bits [7:5], ISR bits [5:4], FCR bits [5:4],
MCR bits [7:5] and MSR [7:0] bits. After a reset, all these bits are set to a logic 0 to be compatible with ST16C550 mode (default).
* Logic 1 = Enables write access to the enhanced function bits: IER bits [7:5], ISR bits [5:4], FCR bits [5:4],
MCR bits [7:5] and MSR [7:0] bits.
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EFR[3:0]: Software Flow Control Select Combinations of software flow control can be selected by programming these bits, as shown in Table 20. TABLE 20: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT [3] 0 0 1 0 1 X X X 1 0 1 0 EFR BIT [2] 0 0 0 1 1 X X X 0 1 1 0 EFR BIT [1] 0 X X X X 0 1 0 1 1 1 1 EFR BIT [0] 0 X X X X 0 0 1 1 1 1 1 TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL No TX and RX flow control (default and reset) No transmit flow control Transmit Xon1, Xoff1 Transmit Xon2, Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2 No receive flow control Receiver compares Xon1, Xoff1 Receiver compares Xon2, Xoff2 Transmit Xon1, Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon2, Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 No transmit flow control Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Software flow control can not be used when the Auto RS-485 Half-Duplex Direction Control feature is enabled (FCTR[5]=1). With this feature enabled, the RTS#/DTR# output controls the direction of the half-duplex RS485 transceiver. The RTS#/DTR# output changes the direction of the half-duplex transceiver to the transmit mode when data is being transmitted from the UART on the TX output. However, the RTS#/DTR# output will remain in the receive direction if the TX FIFO is empty and the RX FIFO triggers an XON or XOFF character to be transmitted. 4.15 TXCNT[7:0]: Transmit FIFO Level Counter - Read Only Transmit FIFO level byte count from 0x00 (0 bytes) to 0xFF (255 or 256 bytes). This 8-bit register gives an indication of the number of characters in the transmit FIFO. The FIFO level Byte count register is read only. The user can take advantage of the FIFO level byte counter for faster data loading to the transmit FIFO, which reduces CPU bandwidth requirements. 4.16 TXTRG [7:0]: Transmit FIFO Trigger Level - Write Only An 8-bit value written to this register sets the TX FIFO trigger level from 0x00 (zero) to 0xFF (255). The TX FIFO trigger level generates an interrupt whenever the data level in the transmit FIFO falls below this preset trigger level. 4.17 RXCNT[7:0]: Receive FIFO Level Counter - Read Only Receive FIFO level byte count from 0x00 (0 bytes) to 0xFF (255 or 256 bytes). It gives an indication of the number of characters in the receive FIFO. The FIFO level byte count register is read only. The user can take advantage of the FIFO level byte counter for faster data unloading from the receiver FIFO, which reduces CPU bandwidth requirements.
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XR17V354
4.18
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART RXTRG[7:0]: Receive FIFO Trigger Level - Write Only
An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0xFF (255). The RX FIFO trigger level generates an interrupt whenever the receive FIFO level rises to this preset trigger level. 4.19 4.20 XOFF1, XOFF2, XON1 AND XON2 REGISTERS - Write Only XCHAR REGISTER - Read Only These registers are used to program the Xoff1, Xoff2, Xon1 and Xon2 control characters respectively. This register gives the status of the last sent control character (Xon or Xoff) and the last received control character (Xon or Xoff). This register will be reset to 0x00 if, at anytime, the Software Flow Control is disabled. XCHAR [7:4]: Reserved XCHAR [3]: Transmit Xon Indicator If the last transmitted control character was a Xon character or characters (Xon1, Xon2), this bit will be set to a logic 1. This bit will clear after the read. XCHAR [2]: Transmit Xoff Indicator If the last transmitted control character was a Xoff character or characters (Xoff1, Xoff2), this bit will be set to a logic 1. This bit will clear after the read. XCHAR [1]: Xon Detect Indicator If the last received control character was a Xon character, Xon characters (Xon1, Xon2) or an Xon-Any character, this bit will be set to a logic 1. This bit will clear after the read. XCHAR [0]: Xoff Detect Indicator If the last received control character was a Xoff character or characters (Xoff1, Xoff2), this bit will be set to a logic 1. This bit will clear after the read.
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PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART TABLE 21: UART RESET CONDITIONS
REGISTERS DLL DLM DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TXCNT TXTRG RXCNT RXTRG XCHAR XON1 XON2 XOFF1 XOFF2
RESET STATE Bits [7:0] = 0x01 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0xXX Bits [7:0] = 0xXX Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x01 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x60 Bits [3:0] = logic 0 Bits [7:4] = logic levels of the inputs Bits [7:0] = 0xFF Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00
I/O SIGNALS TX[3:0] IRTX[3:0] RTS#[3:0] DTR#[3:0] EECK EECS EEDI
RESET STATE HIGH LOW HIGH HIGH LOW LOW LOW
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XR17V354 ABSOLUTE MAXIMUM RATINGS
Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (176-FPBGA)
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
3.6 Volts -0.5 to VCC+0.5V -40o to +85o C -65o to +150o C 500 mW theta-ja = TBD, theta-jc = TBD
ELECTRICAL CHARACTERISTICS (TBD)
DC ELECTRICAL CHARACTERISTICS TA=-40O TO +85OC (INDUSTRIAL GRADE) SUPPLY VOLTAGE, VCC = 3.3V
SYMBOL VIL VIH VOL VOH ICC PARAMETER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Supply Current 2.4 120 MIN -0.3 2.4 MAX 0.6 VCC33 0.4 UNIT
S
CONDITION
NOTES
V V V V mA IOL = 6 mA IOH = -4mA Total for all VCC33 power supplies
64
PRELIMINARY
REV. P1.0.2
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
PACKAGE DIMENSIONS (176-FPBGA)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1 A B C D E F G H J K L M N P R
A1 corner
D
D1
D1 D
(A1 corner feature is mfger option)
Seating Plane A A1 A2
b
e
NOTE: Note: The control dimension is the millimeter column INCHES SYMBOL A A1 A2 D D1 b e MIN 0.047 0.010 0.037 0.508 MAX 0.059 0.014 0.045 0.516 MILLIMETERS MIN 1.20 0.25 0.95 12.90 MAX 1.50 0.35 1.15 13.10
0.441 BSC 0.018 0.022
11.20 BSC 0.45 0.55
0.031 BSC
0.80 BSC
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XR17V354
PRELIMINARY
REV. P1.0.2
HIGH PERFORMANCE QUAD PCI-EXPRESS UART REVISION HISTORY
DATE March 2009 April 2009 July 2009 REVISION P1.0.0 P1.0.1 P1.0.2 Preliminary Datasheet. DESCRIPTION
Fixed typo in Pin Descriptions. G12 should be "VCC12" as shown in Figure 2 and not "VCC33". Added preliminary DC Electrical Characteristics. Clarified VCC33 and VCC12 pin descriptions.
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2009 EXAR Corporation Datasheet July 2009. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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